ONO Gate Insulation Layout to Prevent Electron Trapping
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Solution Overview
Problem
Unwanted electron trapping occurs in the nitride sublayer of the ONO insulation layer above the STI isolation regions during program operations in non-volatile memory cells, leading to reduced data retention and cell current drift, particularly affecting MLC and analog data storage applications.
Innovation Solution
Forming a compound insulation layer with a nitride sublayer between oxide sublayers, and selectively removing the nitride sublayer from isolation regions to prevent electron trapping, while maintaining it between floating and control gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC and analog data storage applications are implemented, then storage capacity is increased, but sensitivity to electron trapping and cell current drift is increased
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing electron trapping before it can occur during program operations. By omitting the nitride sublayer in isolation regions above STI, the structure pre-eliminates the trapping sites that would otherwise capture electrons during operation. This preventive measure is particularly critical for MLC and analog applications where even minor electron trapping would cause unacceptable cell current drift and compromise data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents electron trapping in the isolation regions, enhancing data retention and reducing cell current drift, thereby improving the performance of non-volatile memory cells, especially in MLC and analog storage applications.
Implementation Method 1
Non-volatile memory cell with ONO compound insulation layer between floating and control gates and a method of fabrication... preventing electron trapping in dielectric between floating gates
Data Source
AI summary
A method comprises forming a first insulation layer on an upper surface of a semiconductor substrate, forming a first conductive layer on the first insulation layer, and forming a compound insulation layer on the first conductive layer, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer. A second insulation layer is formed on the compound insulation layer. A trench is formed that extends through the second insulation layer, the compound insulation layer, the first conductive layer, the first insulation layer, and into the semiconductor substrate. The trench is filled with fill insulation material. The second insulation layer and an upper portion of the fill insulation material are removed. A second conductive layer is formed on the compound insulation layer, and on the fill insulation material in the trench.