ONO Structure Fabrication for NAND Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for manufacturing oxide on nitride on oxide (ONO) structures in Flash memory devices face challenges in achieving smaller device sizes with faster switching speeds and higher complexity, requiring complex processes and structures that are difficult to manufacture and integrate.
Innovation Solution
A method and structure for manufacturing ONO structures in Flash memory devices, involving a semiconductor substrate with a gate dielectric layer, floating gate layers, a trench region filled with dielectric material, and an oxide on nitride on oxide layer, along with a control gate, which includes a planarization process and a selective removal step using HF dipping to enhance the ONO and polysilicon contact area, thereby increasing the control gate-floating gate coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional methods are used to manufacture ONO structures, then device size can be reduced, but manufacturing complexity increases and device yields decrease
Solution Approach 1:
The patent divides the ONO structure fabrication into distinct segments: forming the oxide layer, depositing the nitride layer, and forming the second oxide layer with controlled thickness. This segmentation allows each layer to be optimized independently, reducing overall manufacturing complexity while enabling smaller device sizes.
Solution Approach 2:
The patent performs preliminary planarization of the substrate before forming the ONO structure, and preliminarily forms the oxide layer with specific thickness control before nitride deposition. These preliminary actions establish a controlled foundation that simplifies subsequent processing steps and improves manufacturing yields.
2Productivity
If device size is reduced to increase circuit density, then more devices can be fabricated per wafer, but switching speed and signal clarity deteriorate
Solution Approach 1:
The patent changes critical parameters including the oxide layer thickness (controlled to specific ranges), nitride layer composition, and deposition conditions to optimize switching speed. By precisely controlling these parameters, the patent maintains fast switching performance even as device size decreases and circuit density increases.
Solution Approach 2:
The patent uses a composite ONO structure combining oxide and nitride materials with specific properties. The oxide layers provide insulation and charge storage, while the nitride layer provides tunneling characteristics, creating a composite structure that maintains excellent switching performance at smaller device dimensions.
3Area of moving object
If complex manufacturing processes are used to achieve smaller device sizes, then device density increases, but manufacturing precision and yield decrease
Solution Approach 1:
The patent employs self-aligned processes where the ONO structure formation is automatically aligned with the device geometry without requiring additional complex alignment steps. The oxide and nitride layers self-align to the substrate features, reducing manufacturing precision requirements and improving yields while enabling smaller device areas.
Solution Approach 2:
The patent replaces complex mechanical alignment and positioning systems with deposition-based self-alignment mechanisms. The chemical vapor deposition and atomic layer deposition processes naturally conform to the substrate topology, eliminating the need for precise mechanical positioning and reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher device yields, improved program/erase speeds, and compatibility with conventional technology, allowing for higher contact areas between the ONO and floating gate structures, leading to increased control gate-floating gate coupling ratios and desirable properties such as faster programming and erasing.
Implementation Method 1
a selective removal step using HF dipping to enhance the ONO and polysilicon contact area
Data Source
AI summary
A method of processing a flash memory device provides a semiconductor substrate including a surface region and forming a gate dielectric layer overlying the surface region. The method forms a floating gate layer having a thickness and including a first floating gate structure overlying a first portion of the gate dielectric layer and a second floating gate structure overlying a second portion of the gate dielectric layer. The method forms a trench region interposed between the first and second floating gate structures and extending through the entire thickness and through a portion of the surface region into a depth of the substrate. The method fills the entire depth of the trench region in the substrate and a portion of the trench region over the substrate using a dielectric fill material. The method forms an oxide on nitride on oxide (ONO) layer overlying the first and second floating gate structures and the dielectric material and a control gate overlying the ONO layer.