Selective ONO Removal for Accurate Thermal Control
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Solution Overview
Problem
Conventional semiconductor techniques using tube furnace processes result in oxide-nitride-oxide layers on both surfaces of a wafer, leading to obstructed heat energy transmission, misjudged temperature during rapid thermal processes, and subsequently, memories with higher resistance than standard ranges, causing decreased yield and potential scrapping of products.
Innovation Solution
A method is developed to form a semiconductor structure with a nitride mask layer on one ONO layer, allowing selective removal of the second ONO layer on the back surface, preventing overheating during rapid thermal processes, and forming a third ONO layer with a fifth oxide layer on the first nitride layer, which is then patterned for memory formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an oxide-nitride-oxide layer is formed by a tube furnace process on both surfaces of a wafer, then the layer formation is complete and uniform, but the heat energy transmission is obstructed, causing misjudged temperature during rapid thermal processes
Solution Approach 1:
The patent removes the oxide-nitride-oxide layer from the back surface of the wafer through selective etching processes. This extraction eliminates the harmful thermal insulation effect on the back surface while preserving the functional ONO layer on the front surface, thereby resolving the temperature measurement accuracy issue without compromising the front surface layer formation quality
Solution Approach 2:
The patent segments the wafer into front surface and back surface regions, applying different treatments to each. The front surface retains the complete ONO layer for device functionality, while the back surface has the ONO layer selectively removed to allow proper heat transmission. This segmentation enables simultaneous optimization of both layer formation quality and temperature control
2Measurement precision
If the process temperature is heated to an over-high temperature to compensate for misjudgment, then the temperature measurement issue is addressed, but the memory resistance becomes higher than the standard range
Solution Approach 1:
By removing the back surface ONO layer, the patent eliminates the thermal insulation that caused temperature misjudgment. This allows the rapid thermal process to accurately control the front surface temperature without compensatory overheating, thereby maintaining memory resistance within the standard range while achieving accurate temperature control
3Measurement precision
If the oxide-nitride-oxide layer on the back surface is removed, then the heat energy transmission is improved and temperature control is accurate, but additional process steps are required
Solution Approach 1:
The patent applies a nitride mask layer to the front surface ONO layer before the selective removal process. This preliminary masking action protects the functional front surface layer while allowing the back surface layer to be removed through subsequent etching steps, making the selective removal process feasible and controllable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents overheating during thermal processes, reduces memory resistance within standard ranges, and enhances product yield and efficiency by ensuring accurate temperature control and proper ONO layer formation.
Implementation Method 1
A nitride mask layer is formed on the first ONO layer
Implementation Method 2
The fourth oxide layer is removed
Implementation Method 3
The second nitride layer and the nitride mask layer are removed
Implementation Method 4
The second oxide layer and the third oxide layer are removed
Implementation Method 5
A fifth oxide layer is formed on the first nitride layer
Data Source
AI summary
A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.