ONO Stack ALD Integration for SONOS Charge Retention

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Solution Overview

Problem

The challenge in scaling SONOS memory cells for analog memory and processing is exacerbated by issues such as charge retention in the ONO stack, threshold voltage degradation, and migration, which are not effectively addressed by current fabrication processes.

Innovation Solution

A customizable oxide-nitride-oxide (ONO) stack fabrication process is integrated into the baseline CMOS process flow, utilizing atomic layer deposition (ALD) to form a multi-layer charge trapping layer with varying oxygen richness levels, and a blocking dielectric layer to enhance charge retention and reduce leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used for SONOS memory cells, then manufacturing simplicity is maintained, but charge retention in the ONO stack deteriorates and threshold voltage degradation occurs

Engineering Contradiction:

Improvecharge retentionVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The charge trapping layer is divided into multiple sub-layers with different oxygen richness levels, allowing each sub-layer to be independently optimized for charge retention while maintaining compatibility with standard CMOS fabrication processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the charge trapping layer are given different oxygen concentrations to create localized properties that enhance charge retention in specific areas while maintaining overall process simplicity

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If standard CMOS process flow is used, then manufacturing compatibility is maintained, but compositional control of the ONO stack is insufficient

Engineering Contradiction:

Improvecompositional controlVSAvoidprocess integration complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The oxygen concentration parameter is varied within the charge trapping layer to create multiple sub-layers with different compositions, enabling precise control of the ONO stack properties while using standard ALD equipment and CMOS-compatible processes

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The charge trapping layer is formed as a composite structure with multiple sub-layers having different oxygen richness levels, combining the benefits of varied composition for improved control with the simplicity of single-process fabrication

Inventive Principle:

Principle #40Composite materials

3Quantity of substance

If multiple-level SONOS memory cells are implemented for analog memory, then storage capacity increases, but threshold voltage migration and charge retention issues worsen

Engineering Contradiction:

Improvestorage capacityVSAvoidthreshold voltage stability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The charge trapping layer is segmented into multiple sub-layers that can independently trap charges at different levels, enabling multi-level storage while the varied oxygen richness prevents charge migration and maintains threshold voltage stability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different sub-layers are optimized with specific oxygen concentrations to create localized charge trapping regions that prevent inter-layer charge migration, enabling reliable multi-level storage

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed fabrication process improves the uniformity and compositional control of the ONO stack, leading to enhanced charge retention, reduced threshold voltage degradation, and improved scalability for advanced technology nodes, while maintaining a low thermal budget.

Implementation Method 1

utilizing atomic layer deposition (ALD) to form a multi-layer charge trapping layer

Methodology Applied

Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

performing at least one of a first radical oxidation and a first oxide deposition process steps

Methodology Applied

Scientific EffectRadical oxidation: Oxidation

Data Source

PatentUS20250185250A1Method of forming oxide-nitride-oxide stack of non-volatile memory and integration to CMOS process flow

Publication Date: 2025.06.05 INFINEON TECHNOLOGIES LLC

AI summary

A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxidation or oxide deposition process steps are performed to form tunnel dielectric layer overlying the substrate. Silicon nitride deposition process steps are also performed to form a multi-layer charge trapping (CT) layer in which at least some of the process parameters of silicon nitride deposition process steps are adjusted when forming the first and second CT sub-layers of the multi-layer CT layer. Subsequently, radical oxidation or oxide deposition process steps are performed in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer.