ONO Stack ALD Integration for Stable SONOS Analog Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of SONOS memory cells for multi-level analog memory and processing is hindered by challenges such as charge retention in the ONO stack, threshold voltage degradation, and migration, which affect the precision and reliability of the memory cells.
Innovation Solution
An improved fabrication process for forming ONO stacks in SONOS memory cells is introduced, which involves a customizable process flow using atomic layer deposition (ALD) to form a multi-layer charge trapping layer with varying oxygen richness levels, and a blocking dielectric layer, integrated into a baseline CMOS process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to form ONO stacks in SONOS memory cells, then the manufacturing process is simpler and more established, but the uniformity, thickness control, and compositional precision of the ONO stack deteriorate
Solution Approach 1:
The patent applies parameter changes by utilizing atomic layer deposition (ALD) to precisely control deposition parameters such as temperature, pressure, and precursor flow rates. This enables atomic-level control over the thickness and composition of the oxide and nitride layers in the ONO stack, achieving superior uniformity and precision compared to conventional fabrication methods.
Solution Approach 2:
The patent employs composite materials by creating a multi-layered ONO stack with alternating oxide and nitride layers. Each layer has distinct properties: the oxide layers provide tunneling and blocking functions, while the nitride layers serve as charge trapping regions. This composite structure enables precise control over charge storage characteristics and improves overall device performance.
2Quantity of substance
If the ONO stack is scaled for multi-level analog memory, then the storage capacity increases, but charge retention and threshold voltage stability deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the charge trapping function into multiple discrete nitride layers within the ONO stack. Each nitride layer can independently trap charges at different energy levels, enabling multi-level analog storage while maintaining stability. The segmented structure prevents charge migration between layers and improves threshold voltage retention.
Solution Approach 2:
The patent implements local quality by creating nitride layers with varying compositions and thicknesses at different positions within the ONO stack. This allows optimization of charge trapping characteristics at specific locations, with some layers designed for high-capacity storage and others for stability and retention, thereby achieving both high capacity and reliable charge retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed fabrication process enhances the uniformity, thickness control, and compositional precision of the ONO stack, thereby improving the reliability and precision of multi-level analog memory operations in SONOS cells.
Implementation Method 1
a customizable process flow using atomic layer deposition (ALD) to form a multi-layer charge trapping layer
Implementation Method 2
electrons to tunnel from the channel and trapped in a charge-trapping dielectric layer by Fowler-Nordheim (FN) tunneling
Data Source
AI summary
A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxidation or oxide deposition process steps are performed to form tunnel dielectric layer overlying the substrate. Silicon nitride deposition process steps are also performed to form a multi-layer charge trapping (CT) layer in which at least some of the process parameters of silicon nitride deposition process steps are adjusted when forming the first and second CT sub-layers of the multi-layer CT layer. Subsequently, radical oxidation or oxide deposition process steps are performed in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer.