ONO Stack Integration in CMOS Flow
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Solution Overview
Problem
The integration of non-volatile memory (NVM) transistors and metal-oxide-semiconductor (MOS) transistors in a single chip poses challenges due to differences in fabrication processes, leading to degradation of charge-trapping gate stacks and increased complexity, cost, and reduced yield, particularly in achieving desired threshold voltages and equivalent oxide thickness (EOT) for high voltage I/O transistors.
Innovation Solution
A method is introduced to embed an Oxide-Nitride-Oxide (ONO) or ONONO charge-trapping stack within a CMOS process flow, using a thick gate oxide for HV or HV I/O devices, which involves specific oxidation processes like rapid thermal oxidation (RTO) and in-situ steam generation (ISSG) to control the thickness and reliability of the ONO stack, ensuring it meets requirements without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge-trapping gate stack is formed using materials and processes different from baseline CMOS process flow, then NVM transistor functionality is achieved, but MOS transistor fabrication is detrimentally impacted and process complexity increases
Solution Approach 1:
The patent merges the NVM charge-trapping gate stack formation process with the baseline CMOS process flow by using the same tunnel oxide formation step (RTO or ISSG) for both MOS gate oxide and NVM tunnel oxide, and by forming the nitride layer using standard CMOS deposition equipment. This integration eliminates separate process steps and reduces overall fabrication complexity while maintaining NVM functionality.
Solution Approach 2:
The patent makes the RTO/ISSG oxidation process universal by using it to form both the gate oxide for MOS transistors and the tunnel oxide for NVM devices in a single process step. The same process equipment and conditions serve dual purposes, eliminating the need for separate specialized process lines and reducing device complexity.
2Manufacturing precision
If gate oxide is formed to meet MOS transistor thickness requirements, then MOS transistor performance is ensured, but previously formed charge-trapping gate stack is degraded
Solution Approach 1:
The patent applies preliminary action by forming the nitride charge-trapping layer BEFORE forming the gate oxide in the baseline CMOS flow. This sequence ensures that subsequent gate oxide formation processes (RTO, ISSG, CVD) cannot degrade the charge-trapping layer, as it is already protected by the oxide layers. The tunnel oxide and blocking oxide are formed around the nitride layer in a way that protects rather than degrades it.
Solution Approach 2:
The patent provides beforehand cushioning by forming the tunnel oxide layer before depositing the nitride charge-trapping layer. This tunnel oxide acts as a protective cushion that prevents direct exposure of the charge-trapping layer to harmful processes during subsequent gate oxide formation, maintaining both MOS and NVM device reliability.
3Adaptability or versatility
If multiple mask sets and process steps are added to integrate NVM and MOS fabrication, then both device types can be fabricated, but fabrication expense increases and yield decreases
Solution Approach 1:
The patent applies segmentation by dividing the wafer surface into distinct regions: NVM device regions where the full ONO stack is formed, and MOS device regions where only the gate oxide is formed. This is achieved through selective masking and deposition processes that treat different areas differently, allowing both device types to be fabricated on the same wafer using the same baseline CMOS process flow without requiring additional mask sets.
Solution Approach 2:
The patent enables self-service by using the baseline CMOS process equipment and process steps to automatically handle both NVM and MOS fabrication. The same RTO/ISSG oxidation process, deposition equipment, and annealing steps serve both device types, eliminating the need for separate specialized equipment and process lines, thereby maintaining productivity and reducing costs.
4Manufacturing precision
If high-temperature processes are used to form thick gate oxide for HV I/O transistors, then MOS transistor voltage requirements are met, but trap density in ONO stack increases
Solution Approach 1:
The patent applies local quality by forming the nitride charge-trapping layer with specific compositional characteristics (silicon-rich or oxygen-lean) that make it resistant to thermal degradation. This localized material property ensures that even when high-temperature processes are used later for thick gate oxide formation in HV I/O devices, the charge-trapping layer maintains its integrity and low trap density, meeting both voltage requirements and reliability standards.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the ONO stack meets thickness and reliability requirements without degradation, maintaining the performance of both NVM and MOS transistors, improving threshold voltage uniformity and reducing the impact of high-temperature processes on trap density, thus enhancing the overall integration and yield of the memory cells.
Implementation Method 1
specific oxidation processes like rapid thermal oxidation (RTO) and in-situ steam generation (ISSG) to control the thickness and reliability of the ONO stack
Implementation Method 2
reducing the impact of high-temperature processes on trap density
Data Source
AI summary
A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.