ONO Trap Storage Structure for Memory Manufacturing
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing 1.5 T memory devices due to the complexity and high cost of patterning processes associated with polysilicon floating gates, which require isolation structures and result in a high gate stack topology.
Innovation Solution
The use of an oxide/nitride/oxide (ONO) structure as a trap storage structure in semiconductor devices, allowing for a thinner gate structure without the need for an isolation layer between the floating gate and control gate, simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon floating gate structure is used, then charge storage capability is improved, but gate structure thickness increases and isolation structures are required
Solution Approach 1:
The patent changes the material composition parameters of the gate structure by replacing polysilicon floating gate with an ONO (oxide-nitride-oxide) stack structure. This parameter change allows achieving charge storage capability through the nitride layer's trap states while reducing the overall gate structure thickness and eliminating the need for isolation structures between floating gate and control gate.
Solution Approach 2:
The patent employs a composite material structure consisting of multiple oxide and nitride layers (ONO stack) instead of a single polysilicon material. The nitride layer provides charge trapping capability while the oxide layers provide electrical isolation and structural integrity, achieving the desired functionality with reduced thickness without requiring additional isolation structures.
2Reliability
If polysilicon floating gate with isolation structure is used, then charge storage is achieved, but patterning process complexity increases
Solution Approach 1:
The patent extracts and eliminates the isolation structure from the gate stack configuration. By using the ONO structure where the oxide layers provide sufficient electrical isolation between the charge trapping region and control gate, the separate isolation structure becomes unnecessary, thereby simplifying the patterning process and reducing manufacturing complexity.
3Ease of manufacture
If thinner gate structure is used, then manufacturing cost decreases, but charge storage capability may be compromised
Solution Approach 1:
The patent changes the material parameters by using nitride layer with high trap state density to provide charge storage capability in a thinner structure. The optimized thickness parameters of the ONO layers maintain sufficient charge storage while reducing overall gate thickness, enabling simpler and lower-cost manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the patterning processes, decreases process time, and lowers costs by reducing the gate structure's thickness and complexity, enabling easier integration and reducing power consumption through source side injection programming and Fowler-Nordheim erase methods.
Implementation Method 1
forming a trap storage structure including a first oxide layer, a first nitride layer and a second oxide layer stacked on the substrate in sequence
Implementation Method 2
Fowler-Nordheim erase methods
Implementation Method 3
source side injection programming
Data Source
AI summary
A semiconductor device includes a substrate, a trap storage structure, a control gate, a cap structure, a word line well, a source line, spacers, a gap oxide layer, a word line and a gate oxide layer. The trap storage structure includes a first oxide layer, a nitride layer and a second oxide layer stacked on the substrate. The control gate is directly on the trap storage structure. The cap structure is stacked on the control gate to form a stacked structure. The word line well and the source line are disposed in the substrate at opposite sides of the stacked structure. The spacers are on sidewalls of the stacked structure. The gap oxide layer is on a sidewall of one spacer. The word line is on the word line well and the gap oxide layer. The gate oxide layer is between the word line and the word line well.