On-Chip Scan Control for In-System Semiconductor Testing
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Solution Overview
Problem
Existing ATPG test methodologies for digital semiconductor devices require numerous external pins for testing, limiting their application to production tests before packaging and making post-packaging failure analysis time-consuming and error-prone, especially in safety-critical applications.
Innovation Solution
A semiconductor circuit with on-chip scan chain hardware and bi-directional communication ports that enable in-system scan testing by loading and reading digital test patterns and responses without external pins, using individually addressable scan control registers and a microprocessor for comprehensive testing while mounted on a PCB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous external pins are used for ATPG testing, then scan test coverage is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The patent implements scan control logic that allows the same external pins to serve multiple functions: they can be used for both normal device operation and for ATPG scan testing. The scan control logic selectively configures the device operation mode based on control signals, enabling a single pin to function as either a normal I/O pin or a scan test pin, thereby reducing the total number of external pins required while maintaining comprehensive scan test coverage
2Ease of manufacture
If external pins are used for ATPG testing, then manufacturing test capability is improved, but post-packaging failure analysis capability deteriorates
Solution Approach 1:
The patent introduces an on-chip scan control logic unit that acts as an intermediary between external test equipment and the device's internal logic. This control logic receives test control signals through external pins and internally manages the scan chain operations, allowing failure analysis to be performed by analyzing the control logic's operation rather than requiring direct access to numerous external pins, thus enabling post-packaging failure analysis
3Reliability
If multiple scan chains are used for comprehensive testing, then scan test coverage is improved, but the number of external pins required increases
Solution Approach 1:
The patent implements a scan control logic that can selectively enable and control multiple scan chains through a unified control interface. The control logic receives test control signals and distributes them to appropriate scan chains, allowing multiple scan chains to be managed through a single external pin rather than requiring separate pins for each scan chain, thereby maintaining comprehensive test coverage while reducing the number of external pins required
Data Source
AI summary
A semiconductor circuit comprises a digital circuit portion, which in turn comprises a combinatorial logic block. The semiconductor circuit comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion such as register addresses and/or memory addresses. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion through the scan chain involves writing bit values to inputs of the individually addressable scan control registers and reading bit values from at least one output of an individually addressable scan control register.