ONU Synchronization in 50G-PON Using LDPC and State Machine

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Solution Overview

Problem

In optical networks, particularly in PONs, existing synchronization methods face challenges in achieving quick synchronization while maintaining low false loss and false lock probabilities, especially at higher bit error rates like 3e-2, which affects the efficiency and reliability of data transmission.

Innovation Solution

The proposed solution involves an ONU that decodes an encoded DS PHY frame using the same FEC used for the payload, modifies the synchronization state machine by increasing K and not considering the SFC in the hunt or pre-sync states, and uses LDPC codes based on specific mother codes to improve synchronization speed and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If existing synchronization methods are used in PONs, then synchronization can be achieved, but the synchronization speed is slow and false loss/false lock probabilities remain high even at lower bit error rates

Engineering Contradiction:

Improvesynchronization speedVSAvoidfalse loss and false lock probabilities

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent changes the parameter K (number of consecutive matching patterns required) from its conventional value to a higher value, and modifies the verification process by not considering SFC in hunt or pre-sync states. These parameter changes enable faster synchronization while maintaining reliability even at higher bit error rates like 3e-2

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent segments the synchronization process into distinct states (hunt state, pre-sync state, sync state) with different verification requirements. In the sync state, both PSync pattern matching and SFC verification are required, while in other states only PSync matching is needed, enabling faster state transitions

Inventive Principle:

Principle #1Segmentation

2Loss of time

If the number of DS PHY frames required for synchronization is reduced, then synchronization speed improves, but false loss and false lock probabilities increase

Engineering Contradiction:

Improvesynchronization timeVSAvoidfalse loss and false lock probabilities

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent implements a dynamic synchronization state machine that adapts verification requirements based on the current state. The system requires fewer verification steps during state transitions (hunt to pre-sync) but implements stricter verification (both PSync and SFC) when in the sync state, optimizing both speed and reliability dynamically

Inventive Principle:

Principle #15Dynamics

3Reliability

If conventional FEC decoding is used for SFC field, then error correction is provided, but synchronization speed is reduced due to additional processing time

Engineering Contradiction:

Improveerror correction capabilityVSAvoidsynchronization speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent extracts the SFC verification from the FEC decoding process. Instead of requiring full FEC decoding to verify the SFC field, the system performs a simplified verification that checks only the essential synchronization properties, separating the synchronization function from the error correction function and significantly improving speed

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12149346B2Frame coding and optical network unit (ONU) synchronization in passive optical networks (PONs)

Publication Date: 2024.11.19 HUAWEI TECH CO LTD

AI summary

A method is implemented by an ONU in a 50G-PON. The method comprises receiving an encoded DS PHY frame from an OLT, the encoded DS PHY frame comprises an FEC codeword, the FEC codeword comprises an SFC field and a payload, and the SFC field and the payload are encoded with a same FEC; decoding the FEC codeword using the FEC to obtain a decoded SFC field and the payload; performing a first verification of the decoded SFC field while in a sync state of a synchronization state machine; and staying in the sync state when the first verification is successful or exiting the sync state when the first verification is unsuccessful.