Out-of-band FPGA Bitstream Programming via BMC

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In data center environments, particularly with Rack Scale Design (RSD), the challenge arises in programming Field Programmable Gate Arrays (FPGAs) before the operating system is launched, as conventional methods require OS involvement, which is not feasible in virtualized setups where resources need to be configured prior to OS launch.

Innovation Solution

Implementing out-of-band (OOB) management of FPGA bitstreams using mechanisms that do not rely on the operating system, such as PCIe links and BMC/BIOS, to program FPGAs prior to OS boot, enabling pre-OS resource allocation and efficient compute-intensive operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional in-band management methods are used to program FPGAs, then the FPGA can be programmed with bitstreams, but the operating system must be running which prevents pre-OS resource allocation and reduces productivity in virtualized environments

Engineering Contradiction:
Improvetime to program FPGAVSAvoidresource allocation efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent implements out-of-band management that enables FPGA bitstream programming before the operating system is launched. The baseboard management controller (BMC) programs the FPGA during system initialization or boot phase, allowing resource allocation to occur prior to OS launch. This preliminary action eliminates the requirement for OS involvement in FPGA programming, thereby reducing time loss and improving resource allocation efficiency in virtualized data center environments.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If out-of-band management is implemented to program FPGAs before OS launch, then resource allocation efficiency improves, but the device complexity increases due to additional management controllers and interfaces

Engineering Contradiction:
Improveresource allocation efficiencyVSAvoidmanagement system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a baseboard management controller (BMC) as an intermediary device that handles FPGA bitstream programming independently of the operating system. The BMC communicates with the FPGA through dedicated out-of-band interfaces, acting as a mediator between the management system and the FPGA. This intermediary approach enables pre-OS resource allocation while consolidating management functions in a dedicated controller, thereby improving productivity without excessively increasing overall system complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If FPGAs are programmed using OS-dependent methods, then the programming process is simplified, but the adaptability to virtualized environments and dynamic re-composition requirements is reduced

Engineering Contradiction:
ImproveFPGA programming simplicityVSAvoidplatform re-composition capability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent segments the FPGA programming function from the operating system by implementing out-of-band management through the BMC. This segmentation separates the bitstream programming operation from OS-dependent processes, allowing the FPGA to be programmed independently during system initialization. The separation enables the system to adapt to virtualized environments and perform dynamic re-composition of computing platforms, as the FPGA can be reprogrammed without requiring OS intervention, thereby improving both adaptability and operational flexibility.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11831486B2Out-of-band management of FPGA bitstreams
Publication Date: 2023.11.28 INTEL CORP
  • US11831486B2 patent drawing
  • US11831486B2 patent drawing
  • US11831486B2 patent drawing

AI summary

Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.