OOK Modulator Circuit With Reduced Gate Swing for Lower Jitter

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Solution Overview

Problem

On-off keying (OOK) modulation circuitry in digital isolators introduces variations such as jitter and intersymbol interference (ISI) in the carrier signal due to the speed of data transmission and variations within circuit components, which affect the accuracy of signal transmission across isolation barriers.

Innovation Solution

The implementation of an OOK modulator circuitry that includes current mirror and level shifter circuitry to reduce the range of gate voltage and minimize the rise and fall time of digital input signals, thereby reducing variations in the modulated carrier signal, comprising transistors configured to enable and disable switches at faster rates and within optimized voltage thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional OOK modulation circuitry is used to modulate digital signals onto carrier signals, then signal transmission across isolation barriers is enabled, but variations such as jitter and intersymbol interference are introduced in the carrier signal

Engineering Contradiction:
Improvesignal transmission accuracyVSAvoidjitter and intersymbol interference
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the voltage range parameter by which the OOK modulator switches between logic states. Specifically, it uses a reduced gate voltage swing (e.g., from 0-5V to 0-1.8V or similar optimized range) to minimize the rise and fall times of the carrier signal, thereby reducing jitter and intersymbol interference while maintaining reliable signal transmission across the isolation barrier

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the speed of data transmission is increased through OOK modulation, then transmission efficiency is improved, but variations and distortions in the carrier signal increase

Engineering Contradiction:
Improvedata transmission speedVSAvoidcarrier signal quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent optimizes the gate voltage swing parameter to enable faster switching speeds while maintaining signal quality. By reducing the voltage range over which the modulator transitions between logic states, the carrier signal can switch more rapidly (improving data transmission speed) without introducing excessive jitter or intersymbol interference (maintaining carrier signal quality)

Inventive Principle:
Principle #35Parameter changes

3Speed

If the range of gate voltage in OOK modulator is reduced to minimize rise and fall time, then switching speed is improved and variations are reduced, but voltage control precision requirements increase

Engineering Contradiction:
Improveswitching speedVSAvoidvoltage control precision
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent changes the gate voltage swing parameter to a smaller, optimized range that enables faster switching speeds. This reduced voltage range minimizes the time required for the carrier signal to transition between logic states (improving switching speed) while the circuit is designed with appropriate precision control mechanisms to maintain accurate voltage control within this narrower range

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11863360B2Methods and apparatus to reduce variations for on-off keying transmissions
Publication Date: 2024.01.02 TEXAS INSTRUMENTS INC
  • US11863360B2 patent drawing
  • US11863360B2 patent drawing
  • US11863360B2 patent drawing

AI summary

An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.