OOO Processor Pipeline Reconfiguration via Phase Training
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Solution Overview
Problem
Conventional out-of-order (OOO) computer processors face challenges in reducing power consumption in their back-end pipelines without degrading performance, especially in phases with low instruction-level parallelism or high branch misprediction, leading to increased power consumption and reduced battery life.
Innovation Solution
A pipeline reconfiguration circuit that generates phase identifiers based on committed instructions and path history to access a pipeline configuration prediction table, performing training cycles to determine optimal pipeline configurations for each phase, thereby reconfiguring the execution pipeline to improve power efficiency while minimizing performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the back-end pipeline is overprovisioned to extract maximum performance in all program phases, then processor performance is improved, but power consumption increases
Solution Approach 1:
The pipeline reconfiguration circuit dynamically selects between multiple pipeline configurations (e.g., different issue widths, reservation station bank configurations) based on the detected phase characteristics. This allows the pipeline to adapt its performance level to match the actual workload requirements, avoiding the static overprovisioning that causes excessive power consumption while maintaining high performance when needed.
Solution Approach 2:
The system changes key pipeline parameters such as issue width and reservation station configuration based on phase identification. By modifying these parameters according to the detected program phase (e.g., branch-heavy phases vs. parallel execution phases), the system optimizes the balance between performance and power consumption for each specific workload scenario.
2Use of energy by moving object
If the back-end pipeline performance is reduced to lower power consumption, then power consumption is reduced, but processor performance degrades
Solution Approach 1:
Rather than using a fixed reduced-performance configuration, the system dynamically adjusts pipeline capabilities to match actual workload demands. The pipeline reconfiguration circuit detects phase characteristics and selects appropriate configurations, ensuring performance is only reduced when the workload actually requires lower performance, thus avoiding unnecessary performance degradation.
Solution Approach 2:
The system selectively modifies pipeline parameters based on detected phase characteristics. For example, during branch-heavy phases where parallel execution is limited, the issue width may be reduced to save power, while during parallel execution phases, full performance is restored. This selective parameter adjustment avoids blanket performance reduction.
3Use of energy by moving object
If conventional power-saving techniques are applied to reduce back-end pipeline power consumption, then power consumption is reduced, but instruction processing capability is lost
Solution Approach 1:
The pipeline reconfiguration circuit enables dynamic adaptation of the back-end pipeline to actual workload characteristics. By detecting phase properties (such as branch frequency, instruction-level parallelism potential) and selecting appropriate configurations, the system maintains full instruction processing capability when needed while reducing power consumption during phases where full capability is not required, avoiding the permanent capability loss of conventional power-saving techniques.
Data Source
AI summary
Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction is disclosed. In one aspect, a pipeline reconfiguration circuit is communicatively coupled to an execution pipeline providing multiple selectable pipeline configurations. The pipeline reconfiguration circuit generates a phase identifier (ID) for a phase based on a preceding phase. The phase ID is used as an index into an entry of a pipeline configuration prediction (PCP) table to determine whether training for the phase is ongoing. If so, the pipeline reconfiguration circuit performs multiple training cycles, each employing a pipeline configuration from the selectable pipeline configurations for the execution pipeline, to determine a preferred pipeline configuration for the phase. If training for the phase is complete, the pipeline reconfiguration circuit reconfigures the execution pipeline into the preferred pipeline configuration indicated by the entry before the phase is executed.