Out-of-order write circuitry for SoC latency reduction
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Solution Overview
Problem
In computer systems, strict ordering of I/O write cycles can lead to performance degradation due to long propagation delays and unnecessary waiting for acknowledgement signals, especially in large System-On-Chip (SoC) designs where data integrity may not be critical.
Innovation Solution
The implementation of Out-Of-Order Write (OOOW) circuitry in a System-On-Chip (SoC) that allows processors to execute write instructions without waiting for acknowledgement signals by sending imitated acknowledgements, enabling both out-of-order and in-order write modes based on operational settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict ordering of I/O write cycles is enforced, then data integrity is maintained, but processor performance deteriorates due to waiting for acknowledgement signals
Solution Approach 1:
The patent creates a copy of the acknowledgement signal path by introducing an imitated acknowledgement signal generated by the OOOW circuitry. This copy allows the processor to proceed without waiting for the actual acknowledgement from the register, thus improving performance while maintaining the illusion of strict ordering for data integrity requirements.
Solution Approach 2:
The OOOW circuitry acts as an intermediary between the processor and the registers. It intercepts write instructions, generates imitated acknowledgements, and manages the actual write operations to registers independently, thereby decoupling the processor's execution flow from the physical write completion timing.
2Stability of the object's composition
If the processor waits for acknowledgements before issuing next write instructions, then write ordering is maintained, but latency increases
Solution Approach 1:
The OOOW circuitry performs preliminary actions by pre-generating imitated acknowledgement signals before the actual write operations complete. This allows the processor to issue subsequent write instructions without waiting, effectively performing the acknowledgement function in advance to eliminate waiting time.
Solution Approach 2:
The system dynamically switches between two operational modes: strict ordering mode where actual acknowledgements are used, and out-of-order mode where imitated acknowledgements are used. This dynamic adaptability allows the system to optimize for either ordering stability or time efficiency based on operational requirements.
3Speed
If out-of-order write operations are enabled, then processor speed increases, but complexity of the system increases
Solution Approach 1:
The patent segments the write operation handling into two independent paths: one for processing write instructions and generating imitated acknowledgements (handled by OOOW circuitry), and another for actual write execution to registers. This segmentation isolates the complexity to a dedicated circuit module while keeping the processor architecture relatively simple.
Solution Approach 2:
The OOOW circuitry serves as an intermediary layer that manages the complexity of out-of-order operations. It handles the sophisticated logic of tracking write instructions, generating imitated acknowledgements, and managing mode switching, thereby shielding the processor from this complexity while enabling high-speed out-of-order execution.
Data Source
AI summary
A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.