Operational Amplifier Buffer Circuit for Load-Induced Linearity Control

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Solution Overview

Problem

Operational amplifiers experience non-linearity and load-induced offset errors due to modulation when their output is coupled to a load, resulting in mismatch between input and output voltages, especially when feedback configurations are not ideal.

Innovation Solution

Incorporating a current mirror and a buffer circuit with a voltage compensation component to generate a mirrored current, amplify it, and control the load current, thereby reducing offset errors and maintaining linearity by balancing current and voltage gains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the output of the operational amplifier is coupled to a load, then the amplifier can drive external circuits and provide useful output current, but load-induced modulation of the output results in non-linearity between the input voltage and output voltage

Engineering Contradiction:
Improveoutput current driving capabilityVSAvoidlinearity between input and output voltage
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

A buffer circuit is introduced as an intermediary stage between the current mirror and the output circuit. This buffer circuit isolates the current mirror from load-induced variations, preventing non-linearity while maintaining the amplifier's ability to drive external loads. The buffer circuit acts as a mediator that decouples the sensitive current mirror stage from the variable load conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If a simple amplifier configuration is used, then the device complexity is low and ease of manufacture is high, but load-induced offset errors occur and linearity is degraded

Engineering Contradiction:
Improveamplifier circuit structureVSAvoidoffset error and linearity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The amplifier is segmented into distinct functional stages: a current mirror stage for differential input current conversion, a buffer circuit stage for isolation and current amplification, and an output circuit stage for load driving. This segmentation allows each stage to be optimized independently, with the buffer circuit specifically designed to eliminate offset errors and maintain linearity without significantly increasing overall complexity.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If the current mirror is directly connected to the output circuit, then the circuit complexity is reduced, but the current mirror becomes sensitive to load changes causing non-linearity

Engineering Contradiction:
Improvecircuit configurationVSAvoidstability against load changes
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The buffer circuit serves as a protective intermediary that shields the current mirror from load-induced variations. By placing the buffer between the current mirror and the output circuit, load changes are isolated from the current mirror, ensuring stable and linear operation regardless of load conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8907725B2Circuit to prevent load-induced non-linearity in operational amplifiers
Publication Date: 2014.12.09 ANALOG DEVICES INC
  • US8907725B2 patent drawing
  • US8907725B2 patent drawing
  • US8907725B2 patent drawing

AI summary

Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error.