Op Amp Drive Current Adjuster for LCD Source Driver Slew Rate
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Solution Overview
Problem
Conventional operational amplifiers face limitations in slew rate at the falling edge of the output signal due to the limited driving capability of NMOS transistors, which increases quiescent current and power dissipation, making it undesirable for liquid crystal display (LCD) source drivers.
Innovation Solution
The operational amplifier incorporates a drive current adjuster with specific transistor configurations, including NMOS and PMOS transistors, to adjust the driving current based on output signals, enhancing the slew rate without increasing quiescent current, by using a PMOS transistor as a current source and an NMOS transistor as a current sink, and additional transistors to improve discharge capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the quiescent current of the NMOS transistor Q7 is increased to improve driving capability, then the slew rate at falling edge is improved, but the power dissipation through the output node increases
Solution Approach 1:
The patent applies dynamics by making the quiescent current of the NMOS transistor dynamically adjustable rather than fixed. A control circuit monitors the operating conditions and dynamically adjusts the bias current to match the actual driving requirements, enabling high current only when needed for fast slew rate while maintaining low current during normal operation to reduce power dissipation.
Solution Approach 2:
The patent changes the parameter of quiescent current from a constant value to a variable parameter that can be adjusted based on operating conditions. By implementing a control circuit that modifies the bias current parameter dynamically, the system achieves high slew rate when required while minimizing power consumption during steady-state operation, thus resolving the contradiction between speed and energy use.
2Speed
If the quiescent current of the NMOS transistor Q7 is increased to improve discharge capability, then the slew rate at falling edge is improved, but the static power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of the NMOS transistor's quiescent current through a control circuit that adapts the bias current to actual driving needs. This allows the system to achieve high discharge capability and slew rate only when required, while maintaining low static power consumption during normal operation, effectively resolving the contradiction between speed and energy loss.
Solution Approach 2:
The patent transforms the static quiescent current parameter into a dynamically adjustable parameter. The control circuit modifies the bias current level based on operating conditions, enabling the system to achieve high slew rate performance when needed while minimizing static power consumption during steady-state operation, thus resolving the contradiction between speed and energy loss.
Data Source
AI summary
An operational amplifier includes: a differential amplifier for differentially amplifying first and second differential input signals to generate first and second output signals through first and second nodes; a driver for driving an output node in response to the second output signal; and a drive current adjuster for adjusting a driving current of the driver in response to the first output signal. The drive current adjuster includes: a first transistor including a drain connected to the output node, a gate, and a source connected to a ground voltage; a second transistor including a gate connected to the first node, a drain, and a source connected to a source voltage; a third transistor including a drain connected to the drain of the second transistor, a source, and a gate connected to a first bias voltage; and a fourth transistor including a drain connected to the source of the third transistor, a source connected to the ground voltage, and a gate connected to a second bias voltage, wherein the gate of the first transistor is commonly connected to the drains of the second and third transistors.