Multi-Stage OP-Amp Circuit for Stable High-Voltage Memory Readout
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Solution Overview
Problem
Conventional PMOS transistor-based voltage amplification circuits are inadequate for generating high threshold voltages required in nonvolatile memory devices, especially as the number of bits stored increases, due to breakdown limitations and uneven threshold voltage distributions.
Innovation Solution
An OP-amp circuit design incorporating multiple transistors and resistors, including poly resistors, to generate and amplify drive voltages, ensuring stable output voltages by controlling current flow and voltage levels, utilizing N-type transistors and resistors that adjust according to drive voltages to manage high input voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PMOS transistor-based voltage amplification circuit is used, then the circuit can operate at lower voltages, but it cannot generate high threshold voltages required for multi-bit memory storage due to breakdown limitations
Solution Approach 1:
The voltage amplification function is divided into multiple stages: a first amplification stage using a PMOS transistor for initial gain, and a second amplification stage using an NMOS transistor for final high voltage output. This segmentation allows each stage to operate within its optimal voltage range while achieving the overall high threshold voltage needed for multi-bit memory storage.
Solution Approach 2:
The circuit uses a composite transistor configuration combining both PMOS and NMOS devices in a push-pull arrangement. The PMOS transistor handles the input stage and intermediate amplification, while the NMOS transistor handles the output stage and final voltage boosting, creating a hybrid system that overcomes the breakdown voltage limitations of individual transistor types.
2Quantity of substance
If the number of bits stored in memory increases, then storage capacity improves, but threshold voltage distribution becomes more uneven and exceeds the breakdown voltage of conventional PMOS transistors
Solution Approach 1:
The circuit dynamically adjusts the operating point and gain of each amplification stage based on the input voltage level. The first amplification stage operates at lower voltages with higher gain, while the second stage operates at higher voltages with lower gain, creating a dynamic response that maintains threshold voltage uniformity across different storage capacities.
Solution Approach 2:
The circuit changes the operating parameters (voltage levels, current levels, and transistor biasing) between stages to accommodate the wider threshold voltage range required for multi-bit storage. The PMOS stage operates at lower voltages to maintain precision, while the NMOS stage operates at higher voltages to extend the usable range for increased bit capacity.
3Device complexity
If a single-stage voltage amplification circuit is used, then the circuit design is simpler, but it cannot stably amplify high voltages without current spikes
Solution Approach 1:
The first amplification stage performs preliminary voltage amplification and conditioning before the signal reaches the second stage. This preliminary action prepares the signal by establishing appropriate voltage levels and reducing the risk of current spikes in the final high-voltage output stage, ensuring stable operation.
Solution Approach 2:
The intermediate stage between the PMOS and NMOS amplifiers acts as a buffer that cushions against voltage and current variations. This intermediate stage absorbs potential spikes and instability from the first stage before they reach the second stage, protecting the overall circuit from damage and ensuring reliable high-voltage output.
Data Source
AI summary
An OP-amp circuit includes a first circuit unit configured to generate an operating voltage in response to an enable signal, a second circuit unit configured to amplify a difference between respective voltages received through an inverting terminal and a non-inverting terminal in response to the operating voltage and to output a result of the amplification as a first drive voltage, a third circuit unit configured to output a second drive voltage according to a voltage level of the first drive voltage inputted thereto, and a fourth circuit unit configured to divide an input voltage inputted thereto into a divided voltage according to two resistances having respective resistive values varying according to the first and second drive voltages and to output the divided voltage through an output terminal.