Operational Amplifier Switching Scheme for Lower Input Capacitance
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Solution Overview
Problem
Operational amplifiers face challenges in reducing settling time, which affects their operational speed, particularly in applications like display drivers where increased refresh rates are desired, due to high input capacitance leading to voltage level fluctuations.
Innovation Solution
The operational amplifier design includes a configuration with transistors and switches that allow for selective connection and disconnection of gate nodes to reduce effective input capacitance, utilizing a first output transistor, intermediate transistors, and an input transistor with a load device and output stage to drive voltage based on specific currents, and switches to manage capacitance dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operational amplifier is designed to reduce settling time to enhance operational speed, then the operational speed is improved, but the input capacitance increases causing voltage level fluctuations
Solution Approach 1:
The patent applies dynamics by making the input capacitance variable rather than fixed. Switches dynamically connect or disconnect the gate nodes of intermediate transistors based on operational requirements, allowing the input capacitance to be adjusted in real-time. This dynamic configuration enables the amplifier to achieve fast settling time when needed while maintaining low input capacitance to avoid voltage fluctuations.
Solution Approach 2:
The patent segments the gate nodes of intermediate transistors from the input node using switches. By dividing the capacitance-contributing elements into separately controllable segments, the input capacitance can be selectively reduced by disconnecting certain gate nodes during specific operational phases, thereby minimizing voltage fluctuations while maintaining operational speed.
2Object-affected harmful factors
If switches are used to dynamically connect and disconnect gate nodes to reduce effective input capacitance, then the input capacitance is reduced, but the device complexity increases
Solution Approach 1:
The switches in the patent serve multiple functions: they control input capacitance reduction, manage signal routing between different transistor stages, and enable dynamic reconfiguration of the amplifier circuit. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving effective input capacitance control.
3Ease of operation
If the gate nodes of intermediate transistors are connected to the input node, then the operational amplifier can operate, but the input capacitance increases affecting settling time
Solution Approach 1:
The patent employs periodic action by alternately connecting and disconnecting the gate nodes of intermediate transistors to the input node using switches. During specific time periods, the gate nodes are connected to enable proper amplifier operation, while during other periods they are disconnected to reduce input capacitance and accelerate settling. This periodic reconfiguration resolves the conflict between operational capability and settling time.
Data Source
AI summary
An operational amplifier includes an output transistor having a gate coupled to an output node, at least one intermediate transistor each having a common gate node, an input transistor having a gate coupled to an input node, and a load device coupled to sources of the output transistor, the at least one intermediate transistor, and the input transistor. The operational amplifier further includes an output stage coupled to the output node, configured to drive the voltage on the output node based on currents through the output transistor, the at least one intermediate transistors, and the input transistor. The operational amplifier further includes a first switch coupled between the common gate node of the at least one intermediate transistor and the gate of the input transistor, and a second switch coupled between the output node and the common gate node of the at least one intermediate transistors.