Operational Amplifier Input Pair Switching for Stable Idling Current
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Solution Overview
Problem
Existing operational amplifiers face challenges in maintaining stable idling currents, particularly when the input common voltage is high, leading to insufficient idling current flow and reduced output voltage stability.
Innovation Solution
The operational amplifier incorporates a current generation circuit that increases the reference current when the idling current decreases, ensuring the idling current can be appropriately adjusted. This is achieved by switching between PMOS and NMOS input differential pairs based on the input common voltage, and by using a reference current source that supplies different reference currents for each differential pair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a conventional operational amplifier is used with high input common voltage, then the circuit can operate at high voltage levels, but the idling current becomes insufficient and output voltage stability deteriorates
Solution Approach 1:
The patent implements dynamic switching between PMOS and NMOS input differential pairs based on the input common voltage level. When the input common voltage is high, the NMOS pair is activated; when it is low, the PMOS pair is activated. This dynamic adaptation ensures that the appropriate transistor type is used for each voltage condition, maintaining sufficient idling current and output voltage stability across the full voltage range.
Solution Approach 2:
The patent changes the operational parameters by switching between different transistor types (PMOS and NMOS) depending on the input common voltage level. The NMOS input differential pair is specifically designed to provide sufficient idling current when operating at high input common voltages, while the PMOS pair handles low voltage conditions. This parameter-based switching resolves the contradiction between high voltage operation and stable output.
2Device complexity
If only a single type of input differential pair is used, then the circuit structure is simple, but the idling current cannot be maintained across different input voltage conditions
Solution Approach 1:
The patent segments the input differential pair function into two separate circuits: a PMOS input differential pair and an NMOS input differential pair. Each segment is optimized for specific input common voltage ranges. The PMOS pair handles low voltage conditions while the NMOS pair handles high voltage conditions. This segmentation allows each circuit to be independently optimized, ensuring sufficient idling current across the entire voltage range without excessive complexity.
Solution Approach 2:
The patent creates a universal input stage that can handle both high and low input common voltage conditions by incorporating both PMOS and NMOS differential pairs. The switching mechanism enables the circuit to adapt its functionality based on the voltage level, making the operational amplifier universally applicable across different voltage conditions while maintaining stable idling current. This multi-functionality approach resolves the contradiction between circuit simplicity and current stability.
Data Source
AI summary
An operational amplifier includes: an input circuit including a PMOS input differential pair and an NMOS input differential pair, an operating input differential pair being switchable between the PMOS input differential pair and the NMOS input differential pair; a current generation circuit structured to generate a reference current; and an output circuit through which an idling current that increases according to an increase in the reference current flows, and structured to generate an output voltage according to output signals of the PMOS input differential pair and the NMOS input differential pair. The current generation circuit is structured to make the reference current larger in a case where a decreasing condition of the idling current is satisfied than in a case where the decreasing condition is not satisfied.


