Op-Amp Sampling Circuit for Offset Calibration and Low-Noise Capture

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Solution Overview

Problem

Existing semiconductor device circuits for amplifying and sampling signals face challenges in efficiently performing operational amplifier offset calibration and achieving low noise signal sampling without the need for specific clock signals.

Innovation Solution

The proposed circuit architecture includes an operational amplifier, input and output capacitors, sampling and holding switches, and combined switches, which operate in specific phases to sample and amplify signals in one clock cycle, perform operational amplifier offset calibration, and reduce input sampling capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional separate sampling and amplification circuits are used, then signal processing can be performed, but the device complexity and number of components increase

Engineering Contradiction:
Improvecircuit complexityVSAvoidsignal processing reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent combines the sampling switch and amplification circuit into a single integrated unit where the sampling switch is directly coupled to the amplification circuit. This merging eliminates the need for separate sampling and amplification stages, reducing device complexity while maintaining reliable signal processing through the unified architecture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The amplification circuit is designed to perform multiple functions: it amplifies the sampled signal, performs offset calibration, and operates without requiring specific clock signals. This multi-functionality reduces the overall device complexity by eliminating dedicated components for each function while maintaining processing reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If traditional offset calibration methods are used, then operational amplifier offset can be corrected, but additional clock signals and components are required

Engineering Contradiction:
Improveoffset calibration precisionVSAvoidcalibration circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The offset calibration function is merged into the amplification circuit itself. The calibration circuit is integrated with the amplification stage, allowing offset correction to be performed within the same circuit that performs signal amplification, thereby eliminating the need for separate calibration components and clock signals.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The amplification circuit performs its own offset calibration without requiring external calibration components or additional clock signals. The circuit is designed to automatically correct its own offset errors through integrated calibration functionality, reducing overall device complexity while maintaining calibration precision.

Inventive Principle:
Principle #25Self-service

3Object-affected harmful factors

If high input sampling capacitance is used, then low noise signal sampling can be achieved, but the input sampling capacitance consumes excessive capacity

Engineering Contradiction:
Improvenoise levelVSAvoidinput sampling capacitance
Core Design Contradiction:
Object-affected harmful factorsVSQuantity of substance

Solution Approach 1:

The patent changes the operational parameters of the sampling and amplification circuit to achieve low noise sampling with reduced capacitance. By optimizing the timing and operation of the sampling switch and amplification circuit, the system achieves effective noise reduction without requiring large input sampling capacitance values.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12244279B2Circuit and method to enhance efficiency of semiconductor device
Publication Date: 2025.03.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12244279B2 patent drawing
  • US12244279B2 patent drawing
  • US12244279B2 patent drawing

AI summary

A method of operating a circuit includes providing the circuit, the circuit includes an operational amplifier, a plurality of sampling switches, a plurality of holding switches, and a plurality of combined switches. The method further includes: during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open; during a second phase, causing the plurality of combined switches to be closed; during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.