Operational Amplifier Switching Scheme for Lower RC Delay
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Solution Overview
Problem
Conventional operational amplifiers in source drivers face a bottleneck due to excessive parasitic capacitance, leading to RC delay and limited output speed, which is exacerbated by increasing resolution requirements, making it difficult to achieve high-speed signal propagation.
Innovation Solution
The operational amplifier design incorporates a capacitance decreasing scheme by utilizing a first differential input pair and switches to operate in speed-up and normal driving modes, where the gate terminal of positive input transistors is coupled to the gate terminal of negative input transistors, reducing parasitic capacitance and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple differential input pairs are used to increase resolution, then manufacturing precision is improved, but parasitic capacitance increases causing RC delay
Solution Approach 1:
The patent implements dynamic switching between different input pair configurations based on operating conditions. During display line periods, the circuit dynamically switches to use fewer input pairs (first mode) to reduce capacitance and accelerate signal propagation. During non-display line periods, it switches to use more input pairs (second mode) to achieve higher resolution for image data, thus dynamically adapting to different performance requirements.
Solution Approach 2:
The patent applies periodic switching between two operational modes synchronized with the display refresh cycle. During display line periods (when pixels need rapid updating), the circuit operates in first mode with reduced capacitance. During non-display line periods (when processing image data), it operates in second mode with increased resolution capability. This periodic action aligns the circuit's capacitive characteristics with the temporal requirements of different processing stages.
2Speed
If the number of resistors in the resistor string is reduced to decrease RC delay, then signal propagation speed is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent dynamically adjusts the effective number of resistors in the resistor string based on operating mode. During display line periods, it uses a reduced number of resistors (first number) to minimize RC delay and maximize signal propagation speed. During non-display line periods, it uses a larger number of resistors (second number) to provide finer voltage division steps for high-precision image data processing, thus dynamically optimizing the trade-off between speed and precision.
3Speed
If switch impedance is reduced to decrease RC delay, then signal propagation speed is improved, but device complexity increases
Solution Approach 1:
The patent combines the switching function with the existing input pair selection mechanism. The same switch network that selects between different differential input pairs is also used to control the effective number of resistors in the resistor string. This merging of functions reduces the need for separate switching components, thereby limiting the increase in device complexity while still achieving the goal of reducing RC delay during display line periods.
Data Source
AI summary
An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.