Op-Amp Input Stage Bias Trimming for Zero Offset Drift

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Solution Overview

Problem

Existing operational amplifier trimming techniques for input offset voltage are complex, power-intensive, noisy, and require significant layout area and testing time.

Innovation Solution

An input stage circuit with intentionally mismatched transistors in differential pairs and unequal bias currents, allowing for a novel trimming technique that reduces input offset voltage to zero with minimal power and noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If variable resistors are used for trimming input offset voltage, then input offset voltage can be reduced, but device complexity and layout area increase

Engineering Contradiction:
Improveinput offset voltageVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the trimming function from complex variable resistors and implements it using simple fixed resistors combined with a digital-to-analog converter (DAC). The DAC generates trim currents that are added to the bias currents of the differential pairs, separating the trimming mechanism from the signal path and reducing circuit complexity while maintaining input offset voltage adjustment capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/laser trimming process with an electronic digital trimming system. Instead of physically adjusting resistor values through laser trimming, the system uses a DAC to digitally control trim current levels, which are then converted to voltage adjustments. This substitution reduces layout area and simplifies the manufacturing process while achieving the same trimming objective.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If laser trimming process is used to adjust resistance, then input offset voltage can be minimized, but manufacturing time and complexity increase

Engineering Contradiction:
Improveinput offset voltageVSAvoidmanufacturing efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent implements preliminary action by pre-calculating and pre-setting the trim current values through the DAC during the manufacturing process. The system allows for rapid digital programming of trim values without requiring time-consuming laser trimming operations. This preliminary setup of trim parameters significantly accelerates the manufacturing process while maintaining precise input offset voltage control.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If additional electronic components are added for trimming, then input offset voltage can be trimmed, but power consumption and noise increase

Engineering Contradiction:
Improveinput offset voltageVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent changes the operating parameters of the existing circuit components to achieve trimming functionality. By adjusting the bias currents through the DAC-controlled trim currents, the system modifies the operating point of the differential pairs to compensate for input offset voltage. This parameter-based approach avoids adding power-intensive components while achieving precise trimming through controlled current adjustments.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250088158A1Input stage circuit for an operational amplifier with enhanced input offset voltage trimming capabilities
Publication Date: 2025.03.13 ZJW MICROELECTRONICS NORTH AMERICA INC
  • US20250088158A1 patent drawing
  • US20250088158A1 patent drawing
  • US20250088158A1 patent drawing

AI summary

An input stage circuit for an operational amplifier includes first and second differential pairs connected in parallel between positive and negative input terminals. Each differential pair comprises a pair of transistors that are intentionally and systematically mismatched. The mismatching of each transistor pair creates a pre-trim input offset voltage for the circuit. However, a unique current is utilized to bias each of the first and second differential pairs. By adjusting the differential between the bias currents, a composite input offset voltage is created that combines with the pre-trim input offset voltage to yield a total input offset voltage for the circuit that approaches zero. Additionally, adjusting the differential between the bias currents simultaneously trims the temperature coefficient of the total input offset voltage to zero while using limited power and producing minimal noise.