Reference Voltage Generator Pre-Settling for OP-Amp Settling Delay

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Solution Overview

Problem

In shrinking semiconductor devices, reference voltage generators like band gap reference circuits and low-dropout regulators face challenges with slow OP-amp output settling times during chip power-up, leading to prolonged power-up times and increased power consumption due to heavy RC loads.

Innovation Solution

An OP-amp output pre-settling scheme is introduced, where a pre-settling circuit actively settles the OP-amp output to a threshold drop before stabilization, incorporating a self-control mechanism for power saving and stability, which can be turned off once internal voltages reach a target level, thereby shortening chip wake-up time and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a pre-settling circuit is added to reduce wake-up time, then the settling speed is improved, but the device complexity increases

Engineering Contradiction:
Improvesettling speedVSAvoidcircuit complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The pre-settling circuit performs preliminary voltage settling action before the main stabilization phase. The circuit actively drives the OP-amp output to a threshold drop voltage level during power-up, preparing the system in advance to reduce the time required for full stabilization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The voltage settling process is divided into two distinct phases: a pre-settling phase that rapidly establishes the voltage near the target level, and a subsequent stabilization phase that completes the precise voltage regulation. This segmentation allows each phase to be optimized independently.

Inventive Principle:
Principle #1Segmentation

2Speed

If the pre-settling circuit is kept active continuously, then the settling speed remains fast, but the power consumption increases

Engineering Contradiction:
Improvesettling speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The pre-settling circuit operates periodically rather than continuously. It is activated during power-up events when fast settling is needed and is deactivated during normal operation when the voltage is already stabilized, thereby reducing overall power consumption while maintaining fast settling capability when required.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit transitions from a static, continuously-active design to a dynamic, conditionally-active design. The pre-settling circuit is enabled only under specific conditions (during power-up or when voltage deviation is detected) and disabled during normal operation, optimizing the balance between performance and power consumption.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If the OP-amp output is allowed to settle naturally, then the device complexity remains low, but the wake-up time is prolonged

Engineering Contradiction:
Improvecircuit complexityVSAvoidwake-up time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The pre-settling circuit acts as an intermediary between the power-up event and the final stabilization phase. It provides an intermediate voltage level (threshold drop) that bridges the gap between the initial power state and the final stabilized state, accelerating the transition without requiring complete redesign of the OP-amp or feedback system.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11262778B2Reference voltage generation
Publication Date: 2022.03.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11262778B2 patent drawing
  • US11262778B2 patent drawing
  • US11262778B2 patent drawing

AI summary

A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.