Opaque Layer Topography for Interconnect Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming multi-layered semiconductor interconnect structures using subtractive metal etch is the difficulty in correctly positioning features in an upper layer to align with underlying features, as the underlying features are not visible under the opaque upper metal layer, leading to misalignment and increased failure due to electromigration.
Innovation Solution
A method is developed to create a first surface topography that maps to the underlying features, forming an opaque layer that retains this topography, allowing for the proper alignment of subsequent structures by referencing the visible topography, enabling the formation of high-aspect-ratio semiconductor interconnects with reduced misalignment and electromigration failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If subtractive metal etch is used to form multi-layered interconnect structures, then manufacturing complexity is reduced, but alignment precision deteriorates because underlying features are not visible under the opaque upper metal layer
Solution Approach 1:
The patent introduces an intermediary alignment layer that is transparent to the patterning light but opaque to the subsequent metal layer. This alignment layer contains alignment marks that are visible during photolithography, enabling precise alignment of upper layer features with underlying features while maintaining the benefits of subtractive metal etch processing
Solution Approach 2:
The patent utilizes optical property changes by employing an alignment layer with specific optical characteristics - transparent to patterning light for visibility during alignment, but designed to be covered by the opaque metal layer. This optical contrast enables detection and measurement of alignment without interfering with the final interconnect structure
2Productivity
If feature sizes continue to decrease to increase density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in filling high aspect ratio features
Solution Approach 1:
The patent inverts the conventional approach by using subtractive metal etch instead of additive deposition. Instead of trying to fill high aspect ratio features with metal (which becomes increasingly difficult as features shrink), the method deposits a continuous metal layer and then selectively removes portions that should not be conductive, thereby achieving precise interconnect formation even at high aspect ratios
Solution Approach 2:
The patent extracts the alignment and definition steps from the metal deposition process. By using a separate alignment layer with visible marks for positioning, and then using etch masks to define the final metal pattern, the method separates the alignment function from the metal fill function, enabling precise control of metal feature locations and dimensions
3Reliability
If barrier layer thickness is increased to prevent copper migration, then reliability is improved, but manufacturing precision deteriorates because the barrier layer occupies a greater fraction of the feature
Solution Approach 1:
The patent extracts the barrier function from the interconnect feature itself. By using a subtractive process where metal is deposited as a continuous layer and then etched away where not needed, the barrier layer can be applied as a thin conformal coating on the substrate before metal deposition, rather than requiring thick barriers within each high aspect ratio feature
Solution Approach 2:
The patent performs the barrier layer deposition as a preliminary step before metal layer formation. The barrier layer is deposited conformally on the substrate and lower interconnect structures before the upper metal layer is deposited and patterned, ensuring copper migration prevention is established in advance without consuming valuable vertical space in the final high aspect ratio features
Data Source
AI summary
A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.