OPC Supplementary Active Regions for Contact Landing
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) fabrication lies in the complexity and inefficiency caused by the facet variations in source and drain features, which lead to reduced contact landing windows and potential etching through the active regions, exacerbated by overlay errors during processing.
Innovation Solution
The implementation of optical proximity correction (OPC) features in the integrated circuit design layout, specifically by adding supplementary active region features adjacent to the active regions, increases the contact landing window and reduces facet slope variations, thereby ensuring adequate contact formation and overcoming overlay errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optical proximity correction features are added to increase contact landing window, then contact formation reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by adding supplementary active region features (OPC features) to the layout before fabrication. These features are strategically placed adjacent to active regions to pre-compensate for optical proximity effects and facet slope variations that would otherwise occur during processing, ensuring adequate contact landing windows and preventing etching through the active regions.
2Productivity
If geometry size is decreased to increase functional density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies local quality by introducing supplementary active region features with specific dimensions and positions tailored to local geometric conditions. The OPC features are selectively added based on local facet slope variations and contact spacing requirements, allowing precise control of contact landing windows in critical areas while maintaining scaling benefits elsewhere in the circuit.
Data Source
AI summary
The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.