OPC-Aware IC Layout Optimization via Pre-Calibrated Shape Modifications
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Solution Overview
Problem
Current integrated circuit design automation tools face challenges in implementing small layout changes for performance optimization due to limited choices in cell libraries and the need for optical proximity correction (OPC) recipes, which are often proprietary and process-specific, hindering the realization of full benefits from layout modifications like reduced leakage power.
Innovation Solution
A technology-design interface aware of optical proximity effects and foundry-specific OPC technologies is established, allowing for technology-specific calibration of layout modifications, storing shape modifications in a library that can be applied post-place and route, enabling designers to optimize circuit parameters like leakage current without accessing proprietary OPC recipes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If small layout changes are applied to optimize circuit performance, then circuit performance is improved, but access to OPC recipes is required which are proprietary and process-specific
Solution Approach 1:
The patent pre-calculates and stores the effects of various shape modifications on circuit parameters in a library before the actual design optimization process. This preliminary action eliminates the need for real-time OPC recipe access during layout optimization, as the modification effects are already known from pre-computed data.
Solution Approach 2:
The patent introduces an intermediary library that stores pre-computed relationships between shape modifications and circuit parameter changes. This library acts as a mediator between the designer's optimization goals and the manufacturing process, eliminating the need for direct access to proprietary OPC recipes while still enabling accurate performance prediction.
2Ease of manufacture
If cell library choices are limited for manufacturability, then manufacturability is ensured, but layout change options for optimization are reduced
Solution Approach 1:
The patent separates the cell library into two distinct components: a core library with pre-qualified manufacturable cells, and a modification library with pre-computed shape changes. This segmentation allows designers to start with manufacturable cells and apply optimized shape modifications, thereby maintaining manufacturability while expanding layout change options.
Solution Approach 2:
The patent makes the cell library dynamic by allowing post-placement shape modifications. Instead of a static library with fixed cell options, the system enables continuous adaptation of cell shapes within manufacturing constraints, providing versatility while maintaining ease of manufacture through the pre-computed modification library.
3Loss of energy
If non-uniform gate shape changes are applied, then leakage reduction is achieved, but custom OPC recipe changes are required
Solution Approach 1:
The patent creates a copy of the OPC analysis results and stores them in a reusable library. Instead of requiring custom OPC recipe changes for each non-uniform gate modification, the pre-computed modification effects are copied and applied directly, eliminating the need for repeated custom OPC analysis while achieving leakage reduction.
Data Source
AI summary
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit.