Optical Proximity Correction for Etch Mask Top Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of semiconductor circuits is affected by diffracted or scattered light during plasma etching, leading to inconsistent patterns due to optical proximity effects, which existing OPC processes may not fully address, resulting in potential top loss of the etch mask layer and pattern inaccuracies.
Innovation Solution
A method involving an optical proximity correction process that adjusts the target layout to account for top loss of the etch mask layer by calculating and controlling the threshold light amount and background light intensity, ensuring the etch mask layer is not removed, and performing a patterning process using the post-OPC layout to maintain the thickness of unexposed regions and prevent pattern connection errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an optical proximity correction process is performed to address pattern inconsistency caused by diffracted or scattered light, then pattern accuracy is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent performs optical proximity correction in advance by calculating threshold light amounts and adjusting the target layout before the actual photolithography process. This preliminary adjustment of exposed and unexposed regions prevents top loss during etching, thereby improving pattern accuracy while managing process complexity through upfront computational work.
2Reliability
If the target layout is adjusted to prevent top loss of the etch mask layer by controlling background light intensity, then reliability of the etch mask layer is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameter of background light intensity by adjusting the target layout to ensure that unexposed regions have sufficient thickness to prevent top loss during etching. This parameter adjustment balances reliability improvement with manageable precision requirements by focusing on critical threshold values rather than continuous precision control.
3Manufacturing precision
If the unexposed region thickness is maintained to prevent pattern connection errors, then pattern consistency is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality adjustment by specifically modifying unexposed regions in the target layout where top loss is likely to occur. Instead of uniformly adjusting the entire layout, it focuses computational effort and layout modifications on critical local areas, thereby improving pattern consistency while reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor circuit fabrication by preventing top loss and ensuring accurate pattern formation, maintaining the integrity of the etch mask layer and improving the consistency of semiconductor patterns.
Implementation Method 1
performing an optical proximity correction process to the target layout and generating a post-OPC layout... performing a patterning process using the post-OPC layout... calculating a threshold background light intensity of the etch mask layer based on the threshold light amount
Implementation Method 2
a background light intensity of at least a portion of the unexposed region separating two or more exposed regions of the etch mask layer may be less than the threshold background light intensity... background light that may leak from the exposed regions of the etch mask layer to the unexposed region
Data Source
AI summary
A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.