Optical Proximity Correction for Line Pattern Alignment
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Solution Overview
Problem
As semiconductor devices shrink in scale, achieving precise alignment and reliable interconnections between conductive layers becomes challenging due to critical dimension requirements and alignment deviations, leading to incomplete stacking and performance issues like leakage and reduced process windows.
Innovation Solution
The method involves modifying integrated circuit layouts with parallel line patterns by adding convex and concave portions on either side, using a computer system to ensure complete stacking of interconnect patterns while maintaining critical dimension uniformity and process window integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimension is reduced to meet scaling requirements, then device integration is improved, but alignment precision between layers deteriorates
Solution Approach 1:
The patent applies optical proximity correction (OPC) to pre-modify the line patterns before fabrication, adding convex and concave portions to compensate for anticipated alignment deviations. This preliminary action ensures that even when alignment errors occur during multi-layer fabrication, the interconnect patterns still overlap sufficiently to maintain reliable connections.
Solution Approach 2:
The patent modifies the geometric parameters of line patterns by introducing convex and concave portions with specific dimensions. These parameter changes increase the overlapping area between interconnect patterns, providing a larger process window that tolerates alignment variations while maintaining manufacturing feasibility.
2Ease of manufacture
If conventional line patterns are used without modification, then manufacturing simplicity is maintained, but interconnect reliability deteriorates due to incomplete stacking
Solution Approach 1:
The patent applies local quality modification by adding convex and concave portions only at specific locations where interconnect overlap is critical. The majority of the line pattern remains unchanged, maintaining simple manufacturing processes, while localized modifications ensure reliable interconnect stacking in key areas.
3Reliability
If alignment tolerance is reduced to achieve precise stacking, then interconnect reliability is improved, but process window deteriorates
Solution Approach 1:
The patent uses OPC to pre-compensate for alignment variations by modifying line patterns with convex and concave portions. This preliminary action creates a design that is inherently more tolerant to alignment errors, effectively enlarging the process window without requiring tighter control during fabrication.
Data Source
AI summary
A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.