Optical Proximity Correction for Sub-45nm Line Spacing
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Solution Overview
Problem
Current optical proximity correction (OPC) techniques are inadequate for sub-45 nm technology nodes, leading to poorly shaped or arranged device features in semiconductor integrated circuits, resulting in device performance deterioration and a narrowed process window.
Innovation Solution
An OPC rule is proposed to correct line spacing in mid-end-of-line operations by adjusting the width of stripes in the IC design layout, where the second width is increased by a predetermined amount when the spacing between adjacent stripes exceeds a predetermined value, maintaining the desired breakdown voltage and process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current OPC techniques are used for sub-45 nm designs, then manufacturing process can be maintained, but device features become poorly shaped or arranged resulting in performance deterioration
Solution Approach 1:
The patent applies parameter changes by modifying the width of stripes in the IC design layout based on their spacing relationships. Specifically, when spacing between adjacent stripes exceeds a predetermined value, the width of one or both stripes is adjusted to reduce the spacing. This parameter adjustment ensures that line spacing remains within acceptable ranges for sub-45 nm technology nodes, preventing poor feature arrangement and maintaining device performance while working within existing manufacturing constraints.
2Productivity
If feature size is scaled down to increase functional density, then production efficiency increases and costs decrease, but manufacturing complexity increases and existing OPC methods become inadequate
Solution Approach 1:
The patent implements preliminary action by performing width adjustments on stripes in the design layout before the actual manufacturing process. The method identifies spacing issues in advance and corrects them by modifying stripe widths, ensuring that patterns are optimized for sub-45 nm fabrication before they reach the manufacturing stage. This preliminary correction prevents manufacturing failures and reduces the need for rework, thereby managing processing complexity while maintaining the benefits of scaled-down feature sizes.
3Manufacturing precision
If stripe width is increased to reduce spacing, then line spacing accuracy improves, but stripe width control becomes more challenging
Solution Approach 1:
The patent applies local quality by selectively adjusting the width of specific stripes based on their local spacing conditions rather than applying a uniform adjustment across all stripes. The method identifies individual stripes or pairs of stripes that exceed the predetermined spacing threshold and modifies only those specific elements. This localized approach maintains manufacturing ease by limiting adjustments to where they are actually needed, while achieving precise line spacing control in critical areas of the layout.
Data Source
AI summary
Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.