OPC Mask Layout for Fine-Pitch Connecting Fin Patterns
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Solution Overview
Problem
Current photolithography processes face limitations in forming patterns with fine pitches, hindering the miniaturization of semiconductor elements and increasing chip area, which interferes with the operating characteristics of transistors in different regions.
Innovation Solution
A semiconductor device design featuring a substrate with distinct regions and connecting fin-type patterns, along with a method for fabricating a mask using OPC models to optimize pattern formation, ensuring reduced chip area and preventing transistor interference by adjusting edge placement errors through simulation and displacement of fragments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithography processes are used to form patterns, then manufacturing capability is maintained, but pattern pitch cannot be sufficiently miniaturized due to resolution limits
Solution Approach 1:
The patent applies optical proximity correction (OPC) in advance during mask fabrication to pre-compensate for pattern distortion. By calculating and adjusting the mask pattern dimensions before actual photolithography, the method anticipates and corrects resolution limitations, enabling finer pitch patterns to be formed accurately despite diffraction effects.
Solution Approach 2:
The patent implements a feedback mechanism where simulated pattern formation results are compared with target patterns, and edge placement errors are calculated and used to iteratively adjust mask fragment positions. This closed-loop optimization ensures that the final mask pattern compensates for photolithography resolution limits and produces the desired fine-pitch patterns.
2Area of stationary object
If chip area is reduced to increase integration, then element density increases, but transistor operating characteristics deteriorate due to interference between transistors in different regions
Solution Approach 1:
The patent introduces connecting fin-type patterns as intermediary structures between first and second multi-channel active patterns. These connecting fins act as mediators that maintain electrical connectivity while providing spatial separation, preventing interference between transistors in different regions even when chip area is reduced for higher integration.
Solution Approach 2:
The patent extends the connection between transistor regions in the vertical direction by forming three-dimensional fin structures. Instead of relying solely on planar separation, the connecting fins utilize the vertical dimension to provide isolation and maintain characteristics, enabling reduced chip area without compromising transistor performance.
3Ease of manufacture
If mask pattern is simplified for ease of fabrication, then manufacturing complexity decreases, but edge placement accuracy deteriorates due to uncorrected optical proximity effects
Solution Approach 1:
The patent segments the mask pattern into multiple independent fragments that can be separately optimized and positioned. By dividing the complex corrected pattern into manageable fragments with adjustment regions, the method maintains fabrication simplicity while achieving high edge placement accuracy through precise positioning of each fragment relative to reference patterns.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device comprises a substrate including a first region, a second region, and a connecting region placed between the first region and the second region, a plurality of first multi-channel active patterns placed in the first region of the substrate, a plurality of second multi-channel active patterns placed in the second region of the substrate, a first connecting fin type pattern which is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction, and a field insulating film which is placed on the substrate and covers an upper surface of the first connecting fin type pattern, wherein a width of the first connecting fin type pattern in a second direction decreases and then increases as it goes away from the first region, and the first direction is perpendicular to the second direction.