Optical Proximity Correction Verification via Netlist Comparison
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Solution Overview
Problem
In semiconductor technology, optical proximity correction faces challenges in preventing exposing interference during the exposure process, particularly when pitches are small, leading to issues like circuit shorts or open circuits and suboptimal electric characteristics.
Innovation Solution
A verifying method using a double patterning process and netlist files to merge and compare pre-OPC and post-OPC layouts, ensuring correct optical proximity correction and preventing exposing interference by enlarging pitch, thereby ensuring accurate electronic function verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch is reduced to increase circuit density, then productivity is improved, but exposing interference occurs leading to circuit short or open
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into two separate exposure steps (first exposure and second exposure) with different pitch values. The first exposure uses a larger pitch to avoid exposing interference, while the second exposure uses a smaller pitch to achieve high circuit density. This resolves the contradiction by separating the conflicting requirements of avoiding interference and achieving high density into distinct process stages.
2Manufacturing precision
If optical proximity correction is applied to reduce pitch, then manufacturing precision is improved, but verifying correctness becomes complex
Solution Approach 1:
The patent uses netlist files as digital copies to represent the electrical characteristics of the layout. By extracting netlist information from both the pre-OPC and post-OPC layouts and comparing these digital representations, the verification process is simplified. This copying approach avoids the complexity of directly analyzing the complex geometric transformations while maintaining verification accuracy.
Solution Approach 2:
The patent replaces the traditional geometric/layout-based verification method with an electrical characteristic-based verification method using netlist files. Instead of manually or automatically comparing complex geometric patterns and transformations, the system substitutes this with comparing electrical properties (such as resistance, capacitance, and connectivity) extracted from netlists, significantly simplifying the verification process.
3Reliability
If double patterning process is used to prevent exposing interference, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing optical proximity correction on the layout before the double patterning process. The pre-OPC layout is prepared in advance with corrected patterns that account for expected exposure effects. This preliminary correction simplifies the subsequent double patterning process and ensures that the final post-OPC layout achieves the desired pitch without exposing interference, reducing overall process complexity.
Data Source
AI summary
A verifying method of an optical proximity correction is provided. The verifying method includes the following steps. A first netlist file is extracted from an integrated pre-OPC layout. A first post-OPC layout and a second post-OPC layout are merged to be an integrated post-OPC layout. A second netlist file is extracted from the integrated post-OPC layout. The first netlist file and the second netlist are compared.