Optical Proximity Correction for RIE Lag Compensation
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Solution Overview
Problem
As feature sizes in semiconductor devices decrease, the patterning of conductive lines and other circuit components becomes challenging due to inaccuracies in lithography mask transfer, with existing optical proximity correction (OPC) methods failing to adequately address mask pattern transfer issues, particularly due to reactive ion etch (RIE) lag, where wider features are etched deeper than narrower ones.
Innovation Solution
The method involves determining the amount of RIE lag in a semiconductor device's material layer and adjusting the size of patterns on a lithography mask to partially compensate for this lag, by reducing the width of wider features, thereby reducing the vertical dimensions and cross-sectional area of the etched patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feature sizes are reduced to improve device performance, then device performance is improved, but patterning accuracy deteriorates due to lithography mask transfer inaccuracies
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the mask pattern dimensions before lithography to compensate for expected etching variations. The mask patterns are deliberately modified in advance based on predicted RIE lag characteristics, so that after etching, the final features achieve the desired dimensions despite process variations.
Solution Approach 2:
The patent implements parameter changes by systematically varying mask pattern parameters (width, length, shape) based on the specific features being patterned. Different compensation parameters are applied to different feature types and sizes, allowing optimization of each feature's final dimensions to account for RIE lag effects.
2Manufacturing precision
If conventional OPC methods are used to improve mask transfer, then some pattern accuracy is improved, but RIE lag effects remain unaddressed causing feature depth and area variations
Solution Approach 1:
The patent applies local quality by implementing feature-specific compensation strategies. Different mask pattern adjustments are made for different feature types (e.g., narrow lines vs. wide spaces, isolated features vs. dense arrays) based on their specific RIE lag characteristics. Each region of the mask receives customized compensation parameters tailored to local etching conditions.
3Quantity of substance
If wider features are etched, then more material is removed, but RIE lag causes deeper etching in wider features leading to non-uniform depths
Solution Approach 1:
The patent implements preliminary anti-action by pre-compensating for the harmful RIE lag effect through adjusted mask patterns. The mask patterns are modified in advance to counteract the tendency for wider features to etch deeper, ensuring that after etching, all features achieve uniform depths despite their different widths and material removal quantities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the RIE lag, resulting in more uniform feature depths and reduced sheet resistance across different feature sizes, improving the accuracy and performance of semiconductor devices by minimizing the difference in cross-sectional areas and sheet resistance between narrow and wide features.
Implementation Method 1
determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device
Implementation Method 2
wider features are etched deeper than narrower ones due to RIE lag
Data Source
AI summary
Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.