Semiconductor Mark Layout Using OPC-Corrected Spliced Alignment Sections

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Solution Overview

Problem

The existing semiconductor manufacturing processes lack a uniform method for manufacturing semiconductor marks, resulting in low overall manufacturing efficiency.

Innovation Solution

A method involving the creation of a pattern with a peripheral edge corrected by Optical Proximity Correction (OPC), followed by cutting multiple independent alignment sections and splicing them to form a semiconductor mark with a peripheral edge corrected by OPC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional semiconductor mark manufacturing methods are used, then the manufacturing process can be completed, but the overall manufacturing efficiency is low due to lack of uniform method and required OPC post-processing

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidOPC post-processing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies Optical Proximity Correction (OPC) to the pattern design stage before manufacturing, rather than performing OPC post-processing after mark formation. This preliminary correction of the pattern's peripheral edge ensures that the final semiconductor mark has the desired dimensions without requiring additional time-consuming post-processing steps, thus resolving the contradiction between manufacturing efficiency and time loss.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If multiple independent alignment sections are cut and spliced to form semiconductor mark, then the mark can be formed with OPC-corrected edges, but the process complexity increases

Engineering Contradiction:

Improveperipheral edge correction precisionVSAvoidmanufacturing process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the pattern into multiple independent alignment sections that can be cut and spliced separately. Each section is processed independently with OPC correction applied to the overall pattern design, allowing for precise control of the peripheral edges while maintaining manufacturing feasibility. This segmentation approach resolves the contradiction by enabling high precision through modular processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines multiple independently processed alignment sections into a complete semiconductor mark through splicing. By merging the precisely corrected sections while maintaining their individual OPC-corrected edges, the final mark achieves high manufacturing precision. This combining approach allows the system to benefit from both the precision of individual section processing and the completeness of the full mark structure.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12230584B2Method for manufacturing semiconductor mark, and semiconductor mark

Publication Date: 2025.02.18 CHANGXIN MEMORY TECH INC

AI summary

A method for manufacturing semiconductor mark includes: providing a pattern having a peripheral edge corrected by Optical Proximity Correction (OPC); cutting multiple independent alignment sections from the pattern; and splicing the multiple alignment sections to form a semiconductor mark having a peripheral edge corrected by OPC.