Optical Proximity Correction Using Underlying Layer Topography
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Solution Overview
Problem
Current lithography techniques face challenges in achieving precise alignment and pattern transfer due to variations in underlying layer topography, leading to discrepancies between the target pattern and the final wafer feature, which affects the performance and accuracy of integrated circuit (IC) manufacturing.
Innovation Solution
The implementation of an optical proximity correction (OPC) process that compensates for topographical information of underlying layers by generating a reflectivity correction map and modifying the IC design layout to optimize mask patterns, ensuring that the final wafer feature closely matches the target pattern through rule-based and model-based retargeting techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography techniques are used without considering underlying layer topography, then the manufacturing process is simpler, but the manufacturing precision deteriorates due to variances between target and final wafer features
Solution Approach 1:
The patent applies preliminary action by determining topographical information of underlying layers before performing the OPC process. A reflectivity correction map is generated in advance based on the underlying layer topology, and this correction map is then used to guide the OPC modifications. This allows the OPC process to proactively compensate for topography-induced variations rather than reacting to them afterward, thereby improving manufacturing precision while managing complexity through structured pre-processing.
Solution Approach 2:
The patent implements local quality by applying different OPC modifications to different regions of the IC design layout based on local underlying layer topography. The reflectivity correction map provides location-specific compensation values that are applied only where needed, allowing precise control over pattern formation in areas with varying underlying layer characteristics without uniformly complicating the entire manufacturing process.
2Manufacturing precision
If OPC process compensates for underlying layer topography using reflectivity correction map, then the manufacturing precision improves, but the device complexity increases
Solution Approach 1:
The patent introduces a reflectivity correction map as an intermediary between the underlying layer topography and the OPC process. This correction map serves as a computational mediator that translates complex topographical variations into simplified compensation parameters that can be easily applied during OPC. By using this intermediary representation, the system manages computational complexity while achieving high pattern transfer accuracy.
3Manufacturing precision
If rule-based and model-based retargeting techniques are applied to modify IC design layout, then the lithography printability improves, but the ease of manufacture deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the IC design layout into multiple regions and applying different OPC modifications to each region based on local underlying layer topography. The reflectivity correction map enables the system to identify and segment areas requiring different levels of compensation, allowing precise control over pattern formation while managing fabrication complexity through localized rather than universal modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and accuracy of IC feature patterning by minimizing variances between the target and final wafer features, improving lithography printability and reducing fabrication complexity and costs.
Implementation Method 1
an area of an underlying layer that reflects radiation toward a portion of a photoresist layer
Data Source
AI summary
Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.