Open Bit Line Memory Mat I/O Selection Architecture
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Solution Overview
Problem
The open bit line architecture in semiconductor memory devices, such as DRAMs, leads to complicated I/O line selection and increased area of the memory cell array, particularly when switching between different I/O numbers like 8 bits and 16 bits, due to the need for dynamic selection and switching of read/write amplifiers and buses.
Innovation Solution
The semiconductor device incorporates a configuration where memory mats at the end portions share a sense amplifier array, allowing for simplified control and reduced area usage by allocating main I/O wirings fixedly to these mats, regardless of the I/O number setting, thereby avoiding the complexity and area increase issues associated with traditional open bit line architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the open bit line architecture is employed with selectable I/O numbers, then the data input/output capability is improved, but the I/O line selection becomes complicated and the memory cell array area increases
Solution Approach 1:
The memory cell array is divided into multiple memory mats (first memory mat, second memory mat, third memory mat) with distinct address allocation schemes. End portion memory mats use a different address mapping strategy compared to intermediate memory mats, allowing simplified I/O line selection while maintaining selectable I/O numbers. This segmentation resolves the contradiction by localizing the complexity to specific regions rather than requiring complex switching throughout the entire array.
Solution Approach 2:
Different address allocation methods are applied to different regions of the memory array. The end portion memory mats employ a specialized address mapping where the upper bits of the row address directly select the memory mat, while intermediate memory mats use conventional allocation. This local differentiation allows the system to achieve selectable I/O numbers without requiring complex dynamic switching mechanisms across the entire array.
2Productivity
If the open bit line architecture is employed with selectable I/O numbers, then the data input/output capability is improved, but the memory cell array area increases
Solution Approach 1:
The first and second memory mats at the end portions share common main I/O wirings through fixed allocation rather than requiring dynamic switching. This merging of I/O resources for end portion memory mats eliminates the need for additional switching circuitry and reduces the overall memory cell array area while still supporting selectable I/O numbers. The fixed allocation strategy combines the access paths efficiently without increasing area.
3Adaptability or versatility
If dynamic selection of read/write amplifiers and buses is implemented, then the I/O number selection is enabled, but the control complexity increases
Solution Approach 1:
The main I/O wirings are pre-allocated to specific memory mats based on their positions (end portion vs. intermediate). This preliminary allocation eliminates the need for dynamic switching control during operation. The address decoding logic inherently directs access to the correct pre-assigned I/O wirings, providing I/O number selection capability without requiring complex real-time control mechanisms.
Data Source
AI summary
When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X13 is (0) and X11 and X12 are (0, 0), a second memory mat that is selected when X13 is (1) and X11 and X12 are (0, 0), and a third memory mat that is selected irrespective of a value of X13 when X11 and X12 are (0, 0). When the I/O number is 16 bit, X13 is ignored, and the first to third memory mats are selected when X11 and X12 are (0, 0). In this manner, because the third memory mat is shared between so-called upper side and lower side, control is prevented from becoming complicated and an area is prevented from increasing.