Open Bit Line Multi-Level Dynamic Memory Device
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Solution Overview
Problem
Conventional multi-level dynamic memory devices with a folded bit line structure face challenges in reducing memory cell size below 8 F2/bit, limiting integration level due to coupling noise and structural constraints.
Innovation Solution
The implementation of a multi-level dynamic memory device with an open bit line structure, featuring divided bit lines, sense amplifiers, coupling capacitors, transfer transistors, and isolation transistors, allows for smaller memory cell sizes by equalizing capacitance and optimizing data storage and retrieval processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a folded bit line structure is used, then coupling noise between bit lines and word lines can be eliminated through differential amplification, but memory cell size cannot be reduced below 8 F2/bit
Solution Approach 1:
The bit line is divided into two separate bit lines (first bit line and second bit line) that are physically separated and extend in opposite directions from the memory cell. This segmentation allows the bit lines to be located outside the memory cell block, enabling memory cell size reduction below 8 F2/bit while maintaining the differential amplification noise elimination capability through the sense amplifiers connected to both bit lines.
Solution Approach 2:
The bit line structure transitions from a folded configuration within the memory cell plane to an open configuration where bit lines extend outward in opposite directions. This dimensional reorganization moves the bit lines to opposite sides of sense amplifiers, reducing in-cell area while preserving differential signaling benefits for noise rejection.
2Productivity
If memory cell size is reduced to increase integration level, then more memory cells can be fabricated per unit area, but coupling noise between bit lines and word lines increases
Solution Approach 1:
By segmenting the single folded bit line into two separate open bit lines that extend in opposite directions, the patent enables tighter memory cell packing (below 8 F2/bit) while maintaining adequate spacing between bit lines and word lines. This segmentation reduces capacitive coupling noise despite the reduced cell size and increased integration density.
Solution Approach 2:
The sense amplifiers serve as intermediary components that are positioned between the open bit lines and the readout circuitry. These sense amplifiers perform differential amplification that actively rejects common-mode noise from word line coupling, enabling high integration levels while maintaining signal integrity despite increased noise environments from denser cell packing.
3Area of moving object
If an open bit line structure with divided bit lines is implemented, then memory cell size can be reduced below 8 F2/bit, but device complexity increases due to additional sense amplifiers and coupling capacitors
Solution Approach 1:
The memory cell array is segmented into multiple blocks, each containing sense amplifiers and coupling capacitors that operate independently. This modular segmentation allows the complex open bit line structure with divided bit lines to be managed in discrete units, reducing the perceived overall complexity while enabling memory cell sizes below 8 F2/bit through the distributed architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables memory cell sizes smaller than 8 F2/bit, enhancing integration level and data storage efficiency while maintaining effective data amplification and restoration.
Implementation Method 1
both a bit line and a complementary bit line are located in the same memory cell block, the amount of coupling noise generated between the bit line and a word line is equal to the amount of coupling noise generated between the complementary bit line and the word line. This common-mode noise can be eliminated by a differential amplification operation of a sense amplifier.
Implementation Method 2
a first coupling capacitor connected between the first main bit line and the first sub-bit line and a second coupling capacitor connected between the second main bit line and the second sub-bit line
Data Source
AI summary
A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the word lines and each of the bit lines and stores at least two bits of data; and a plurality of sense amplifiers, each of which amplifies a voltage difference between the bit lines, the bit lines being located at opposite sides of each of the plurality of sense amplifiers.