Open Bit Line Memory Device Noise Equalization
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Solution Overview
Problem
In semiconductor memory devices with an open bit line structure, noise differences between true and false bit lines lead to vulnerability and inaccurate screening of defective cells during write recovery tests, as high-resistance cells may pass as normal due to insufficient charge application and reduced write recovery time.
Innovation Solution
The semiconductor memory device adjusts coupling noise applied to true bit lines to match that of false bit lines during testing by using bit line precharge voltage providers to selectively apply precharge voltages corresponding to the data stored in selected cells, ensuring equal noise levels for improved screenability without reducing write recovery time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the write recovery time is reduced to screen defective cells, then the productivity of the test process is improved, but the measurement precision deteriorates because high-resistance cells cannot be properly identified
Solution Approach 1:
The patent applies preliminary action by pre-charging the false bit line to a voltage level corresponding to the data value before the read operation. This preliminary voltage setup creates a virtual noise effect that enables proper screening of high-resistance cells even when write recovery time is reduced, thereby maintaining measurement precision while improving productivity
2Area of stationary object
If the open bit line structure is used to reduce device area, then the area of the semiconductor memory device is reduced, but the reliability deteriorates due to unequal noise levels between true and false bit lines
Solution Approach 1:
The patent applies equipotentiality by equalizing the noise levels on true and false bit lines through selective pre-charging of the false bit line to match the data value. This creates equivalent potential conditions for both bit lines, ensuring that noise effects are balanced and reliability is maintained despite the area benefits of the open bit line structure
3Reliability
If the folded bit line structure is used to ensure stable operation against noise, then the reliability is improved, but the area of the semiconductor memory device increases
Solution Approach 1:
The patent applies local quality by implementing selective pre-charging only for the false bit line based on the specific data value being read. This localized adjustment of voltage conditions provides the necessary noise immunity locally where needed, rather than requiring the global structural complexity of the folded bit line configuration
Data Source
AI summary
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.