Open Bitline Memory Edge Dummy Block Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration density of semiconductor memory devices is hindered by the necessity of including a dummy cell block, which occupies additional space and contradicts efforts to increase density.
Innovation Solution
A semiconductor memory device with an open bitline memory structure is designed, featuring edge and central sense amplification blocks with differently sized transistors and capacitor blocks to compensate for capacitance imbalances, allowing the removal of the dummy edge block without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy cell block is included to maintain capacitance balance in open BLSA type memory devices, then reliability is improved, but area increases and integration density decreases
Solution Approach 1:
The patent removes the dummy cell block from the memory device structure. Instead of including unnecessary dummy cells that occupy chip area, the invention extracts only the essential capacitance balancing function and implements it through a dedicated capacitor connected to the bitline, thereby eliminating wasted space while maintaining reliability
Solution Approach 2:
The patent applies local quality by providing capacitance balancing only where needed - specifically at the edge sense amplification block where the dummy cell would normally be located. A capacitor is connected to the bitline at this specific location to provide the necessary capacitance, rather than uniformly distributing dummy cells across the entire memory array
2Area of stationary object
If component sizes are reduced to increase integration density, then area is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameter of capacitance provision from distributed dummy cells to a concentrated capacitor element. This allows precise control of the capacitance value through standard capacitor design parameters, making the manufacturing process more predictable and less sensitive to dimensional variations
Data Source
AI summary
A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.