Open Cavity TSV Interposer for WLCSMP Thermal Management
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Solution Overview
Problem
Wafer level chip scale module packages (WLCSMPs) face challenges in heat dissipation and warpage due to the mismatch in thermal expansion coefficients between stacked semiconductor dies and organic substrates, leading to difficulties in handling and structural integrity.
Innovation Solution
The method involves forming an open cavity TSV interposer with a conductive layer and encapsulant to create a semiconductor device package, where the semiconductor die is mounted over a substrate with an insulating layer, and an encapsulant is deposited to cover the substrate, providing electrical routing and thermal management while minimizing warpage through thermal stress relief.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed organic substrate is used in WLCSMP, then the package structure is simple and easy to manufacture, but heat dissipation is poor and warpage occurs due to CTE mismatch
Solution Approach 1:
The patent changes the substrate material from organic to silicon, fundamentally altering the thermal and mechanical parameters. Silicon's high thermal conductivity and CTE matching with semiconductor dies resolve the heat dissipation and warpage issues while maintaining manufacturing feasibility through established TSV processes
Solution Approach 2:
The patent employs a composite structure combining silicon substrate with TSV interconnects and encapsulant materials. This composite approach leverages the advantages of each material: silicon for thermal management and CTE matching, TSV for electrical interconnection, and encapsulant for protection, thereby resolving the contradiction between manufacturing simplicity and thermal performance
2Ease of manufacture
If a fixed organic substrate is used in WLCSMP, then the package structure is simple and easy to manufacture, but structural integrity deteriorates due to warpage
Solution Approach 1:
Changing the substrate material from organic to silicon fundamentally alters the mechanical and thermal parameters. Silicon's CTE matching with semiconductor dies eliminates warpage, ensuring structural integrity while maintaining manufacturing simplicity through compatible processing techniques
Solution Approach 2:
The patent achieves homogeneity in thermal expansion characteristics by using silicon substrate that matches the CTE of semiconductor dies. This uniformity prevents differential expansion and warpage, maintaining structural integrity throughout the package lifecycle
3Productivity
If the lower semiconductor die is thinner than the organic substrate, then device integration is higher, but heat dissipation becomes difficult
Solution Approach 1:
Changing the substrate material to silicon fundamentally alters the thermal conduction parameter. Silicon's high thermal conductivity provides efficient heat pathways that can accommodate thin semiconductor dies, resolving the heat dissipation issue while maintaining high device integration
4Ease of manufacture
If CTE mismatch exists between upper and lower semiconductor die and organic substrate, then manufacturing is easier, but warpage becomes a recurring issue
Solution Approach 1:
Changing the substrate material from organic to silicon fundamentally changes the CTE parameter. Silicon's CTE matches semiconductor dies, eliminating the mismatch that causes warpage while maintaining manufacturing ease through established silicon processing techniques
Solution Approach 2:
The patent achieves homogeneity in thermal expansion characteristics across all layers by using silicon substrate that matches the CTE of semiconductor dies. This uniformity prevents differential expansion forces that cause warpage, ensuring package stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a thinner, more robust semiconductor package with improved heat dissipation and reduced warpage, enhancing the structural integrity and performance of the WLCSMP by aligning the thermal expansion characteristics of the components.
Implementation Method 1
providing electrical routing and thermal management while minimizing warpage through thermal stress relief
Implementation Method 2
forming a conductive layer over the substrates for electrical routing
Data Source
AI summary
A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.