Open-Drain Output Buffer With Floating Wells
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Solution Overview
Problem
Existing semiconductor output buffers with open-drain pull-down transistors face challenges in handling voltage disparities between different operating regions, leading to potential material breakdown due to over-voltage conditions, especially when interacting with external voltage regions exceeding the native supply voltage level.
Innovation Solution
An open-drain output buffer design featuring three NMOS transistors in series coupled to ground, with well-bias selectors providing reverse bias voltages to floating wells, allowing the buffer to withstand external voltages up to twice the native supply voltage level without exposing gate oxides to excessive voltages, and utilizing voltage dividers and bias selectors to manage voltage levels effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors are exposed to elevated external voltages to broaden voltage interaction range, then adaptability improves, but gate oxide breakdown risk increases
Solution Approach 1:
The patent introduces floating wells as intermediary structures between the external high-voltage region and the transistor gate oxides. These floating wells are coupled to the output pad through coupling transistors, creating an intermediate voltage region that protects the gate oxides from direct exposure to elevated external voltages. The floating well potential is controlled to be near the switching voltage levels, acting as a buffer that allows broader voltage interaction while preventing material breakdown.
Solution Approach 2:
The patent segments the voltage protection function by creating separate floating well regions for different transistors exposed to elevated voltages. Each transistor experiencing potential over-voltage conditions has its own dedicated floating well, allowing independent voltage control and protection. This segmentation enables the system to handle a broader range of external voltages while maintaining safe operating conditions for each individual transistor's gate oxide.
2Reliability
If coupling transistors are used to provide well bias, then voltage protection is achieved, but device complexity increases
Solution Approach 1:
The coupling transistors in the patent serve multiple functions: they provide the electrical path for biasing the floating wells, acts as protection elements against over-voltage conditions, and enable the buffer to interface with external voltage regions. By making these transistors multi-functional, the design achieves comprehensive voltage protection without proportionally increasing device complexity, as the same transistors perform several critical roles simultaneously.
3Adaptability or versatility
If floating wells are coupled to output pad for voltage bias, then adaptability to external voltages improves, but manufacturing cost increases
Solution Approach 1:
The patent utilizes parameter changes in the coupling transistors' conductance characteristics, which are triggered by elevated external voltage levels. By designing these transistors with specific conductance properties that activate at certain voltage thresholds, the floating wells are automatically biased appropriately for different external voltage conditions. This parameter-based control enables broad voltage adaptability while using standard CMOS process technologies, avoiding the need for expensive specialized manufacturing processes.
Data Source
AI summary
An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages. By electrical coupling across maximal voltages, the voltage dividers generate reference voltages that induce proper selection of well-bias voltages to the floating wells.