Open-Drain I/O Circuit for 3.3 V Gate Oxide Protection

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Solution Overview

Problem

Conventional output driving circuits for semiconductor devices with medium gate oxide devices fail to maintain reliability when operating with 3.3 V interface voltage, as they struggle to satisfy the required voltage conditions due to the decreased thickness of the oxide layer, leading to potential reliability issues.

Innovation Solution

An improved input/output driving circuit is designed, featuring a three-stage open-drain output structure with a gate control logic that includes PMOS transistors and an internal resistor for feedback voltage regulation, ensuring the gate-source, gate-drain, and drain-source voltages remain within reliable limits even under high voltage conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If medium gate oxide CMOSFETs for 1.8 V operation or thin gate oxide CMOSFETs for 0.9 V operation are used, then high-speed operation and low-supply voltage are achieved, but the circuit cannot operate properly when 3.3 V is applied

Engineering Contradiction:
Improveoperation speedVSAvoidvoltage compatibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The IO circuit is divided into multiple voltage domains with separate transistor units (first transistor unit for 1.8V, second transistor unit for 3.3V). Each unit is independently controlled by control logic that selects which unit to activate based on the detected voltage level, allowing the circuit to adapt to different voltage requirements while maintaining high-speed performance in each domain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit dynamically switches between different transistor units based on the applied voltage level. The control logic detects the voltage and activates the appropriate transistor unit (first unit for 1.8V operation, second unit for 3.3V operation), enabling the IO circuit to adapt its characteristics to match the operating conditions and maintain reliability across different voltage standards.

Inventive Principle:
Principle #15Dynamics

2Speed

If thin gate oxide is used for high-speed operation, then operation speed improves, but reliability deteriorates when high voltage is applied

Engineering Contradiction:
Improveoperation speedVSAvoidvoltage tolerance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

Different transistor units with different gate oxide thicknesses are used in different voltage domains. The first transistor unit uses medium gate oxide for 1.8V operation, while the second transistor unit uses thin gate oxide for 3.3V operation. Each unit is optimized for its specific voltage domain, allowing the circuit to achieve high-speed performance where needed while maintaining reliability in high-voltage conditions through the protective structure of the voltage detection and control mechanism.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12040793B2Memory system
Publication Date: 2024.07.16 SK HYNIX INC
  • US12040793B2 patent drawing
  • US12040793B2 patent drawing
  • US12040793B2 patent drawing

AI summary

An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The pad is for transmitting and receiving signals. The open-drain driving circuit may output a transmission signal to the pad. The high-voltage protection unit may input a received signal from the pad. The control unit may control the open-drain driving circuit and the high-voltage protection unit. The control unit may include a gate control logic, a transmission control logic and an inverter. The gate control logic may receive a voltage of the pad and output a feedback voltage to the open-drain driving circuit. The transmission control logic may receive a clock signal and an enable signal, and transfer a first control signal to the open-drain driving circuit. The inverter may invert the enable signal and transfer an inverted enable signal to the gate control logic.