Open-Drain Multi-Wire Link Clock Recovery from Symbol Transitions
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Solution Overview
Problem
Existing single-ended source synchronous open-drain communication interfaces face limitations in data rate due to the need for a dedicated clock signal and challenges in clock recovery, particularly with open-drain type drivers where rise and fall times differ significantly, affecting reliable transition detection.
Innovation Solution
A method for generating a clock signal by determining transitions in received signals, delaying clock pulses based on preconfigured intervals corresponding to rise and fall times, and calibrating these intervals to ensure reliable sampling of symbol transitions, thereby integrating clock recovery into symbol transitions without slowing data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated clock line is used for timing information, then clock recovery is reliable, but the data transmission rate is limited by the clock frequency
Solution Approach 1:
The patent extracts the clock timing information from the data signal itself by detecting symbol transitions, eliminating the need for a separate dedicated clock line. The receiver detects transitions in the received data symbols to generate clock pulses, thereby separating the clock function from the data transmission channel and enabling higher data rates limited only by the data line frequency.
Solution Approach 2:
The data signal serves dual purposes: transmitting information and providing timing reference. By embedding clock information within the data symbol transitions, the same communication channel carries both data and timing information, maximizing the utilization of the transmission medium and eliminating the need for additional dedicated clock infrastructure.
2Device complexity
If clock is embedded in data symbols, then no dedicated clock line is needed, but transition detection becomes unreliable due to asymmetric rise and fall times
Solution Approach 1:
The patent applies different delay intervals for different transition directions: a first delay interval for rising transitions and a second delay interval for falling transitions. This local differentiation compensates for the asymmetric rise and fall times of open-drain drivers, ensuring that clock pulses are generated at consistent points relative to the actual symbol transitions, thereby maintaining detection reliability without requiring a dedicated clock line.
Solution Approach 2:
The system dynamically adjusts the delay parameter based on the transition direction. By changing the delay interval parameter according to whether the transition is rising or falling, the system compensates for the inherent asymmetry in open-drain driver characteristics, enabling reliable transition detection across both types of transitions.
3Device complexity
If single-rate signaling is used, then system is simple to implement, but maximum data rate is limited by maximum clock frequency
Solution Approach 1:
The patent employs periodic symbol transitions to encode multiple bits of data within each symbol period. By using transition-based encoding where specific transition patterns represent different data values, the system achieves multi-rate data transmission over the same physical medium, increasing the effective data rate beyond what would be possible with simple single-rate signaling while maintaining relatively simple implementation.
Data Source
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AI summary
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire opendrain link by determining a transition in a signal received from the multi-wire opendrain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.