Open-Drain Output Circuit With Timed Low-Level Hold
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Solution Overview
Problem
Conventional open-drain output circuits experience high power dissipation due to continuous operating current during low-level signal durations, which is inefficient in modern semiconductor devices requiring lower power consumption.
Innovation Solution
The proposed output circuit includes a main output section that inactivates after a specific time during low-level signal durations, and a low-level holding section maintains the output node at a low level, reducing power dissipation by minimizing operating current during this period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the transistor N21 is kept ON during low-level signal duration to maintain output at low level, then the output level is maintained, but power dissipation increases due to continuous current flow
Solution Approach 1:
The patent divides the output circuit into two distinct sections: a main output section (N21, R21) that actively drives the output node, and a low-level hold section (N22, R23) that maintains the low level after the main section is inactivated. This segmentation allows the main output transistor N21 to be turned OFF during low-level signal duration while the hold section N22 maintains the output at low level, thereby eliminating continuous current flow through R21 and reducing power dissipation while maintaining output level stability.
2Loss of energy
If the main output section is inactivated early to reduce current, then power dissipation decreases, but signal transition delay increases
Solution Approach 1:
The low-level hold section N22 is designed to be pre-configured and ready to immediately take over when the main output section is inactivated. The hold section includes transistor N22 and resistor R23 that are positioned to quickly establish the low level at the output node without significant delay, allowing the main output transistor N21 to be turned OFF promptly while maintaining signal transition integrity.
Data Source
AI summary
A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.