Open-Drain Interface Circuit With Dynamic Shift Clock Timing
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Solution Overview
Problem
Existing serial interface circuits with open-drain configurations face issues with data transmission accuracy due to rounded pulse edges and varying pulse widths, leading to errors in data reception, especially at high speeds, and require additional complex correction mechanisms in receiving devices, increasing system size and cost.
Innovation Solution
A serial interface circuit that dynamically adjusts the shift clock cycle based on the data sequence, using a data sequence detector and shift clock generator to output data with corrected pulse widths, ensuring accurate data transmission by extending the High-level period and shortening the Low-level period accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant cycle shift clock is used in an open-drain configuration, then the circuit structure is simple, but the data transmission accuracy deteriorates due to rounded pulse edges and varying pulse widths
Solution Approach 1:
The shift clock cycle is made dynamic rather than constant. The cycle length is adjusted based on the data sequence being transmitted, with shorter cycles for consecutive High-level signals and longer cycles for Low-level signals. This dynamic adjustment compensates for the rounded pulse edges caused by the open-drain configuration, maintaining accurate data transmission without increasing overall system complexity.
Solution Approach 2:
The parameter being changed is the shift clock cycle length. The system changes this parameter according to the data sequence pattern, using different cycle lengths for different data conditions. This parameter change directly addresses the pulse width variation problem in open-drain configurations by pre-compensating for the rounding effect.
2Manufacturing precision
If pulse width correction is implemented at the receiving end, then data reception accuracy improves, but system complexity and cost increase due to additional correction mechanisms
Solution Approach 1:
Instead of correcting the pulse width at the receiving end (the conventional approach), the invention inverts the approach by pre-correcting the pulse width at the transmitting end. The shift clock cycle is adjusted before data transmission based on the data sequence, so that the rounded edges are compensated in advance. This eliminates the need for complex correction mechanisms at the receiving end.
Solution Approach 2:
The correction action is performed preliminarily at the transmitting end before data transmission. The system detects the data sequence in advance and adjusts the shift clock cycle accordingly, so that the compensation is already in place when the data is transmitted. This preliminary action eliminates the need for post-reception correction.
3Manufacturing precision
If the shift clock cycle is extended to compensate for rounded edges, then data transmission accuracy improves, but transmission speed decreases
Solution Approach 1:
The shift clock cycle is made dynamic, adjusting its length based on the actual data sequence being transmitted. When consecutive High-level signals are detected (which cause rounding issues), the cycle is extended. When Low-level signals are present (which don't have the rounding problem), the cycle returns to normal length. This dynamic adjustment maintains accuracy where needed while preserving speed where possible.
Solution Approach 2:
The extended cycle length is applied locally only to the specific portions of data transmission where rounding occurs (consecutive High-level signals). Other portions of the data stream use the normal, faster cycle length. This localized application of the correction minimizes the overall impact on transmission speed while maintaining accuracy where it is needed.
Data Source
AI summary
An interface circuit includes a detector to detect a particular pattern from a sequence of output data, a shift clock generator to change a cycle of a shift clock according to the detection result, a shift register section to change a data output width by the shift clock and output it as drive data, and an open-drain output section including an N-channel transistor driven by the drive data and a pull-up resistor. The detector detects a sequence where the current output data is “0” and the next output data is “1”, and the shift clock generator shortens and extends the cycles of the shift clock corresponding to “0” and “1”, respectively.