Open-Loop Clock Buffer and RCD Timing With Phase Interpolator Calibration
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Solution Overview
Problem
Conventional solutions for maintaining constant propagation delay in DDR4 and DDR5 memory interfaces, such as PLL/DLL, are complex, power-intensive, and face bandwidth limitations, especially at higher data rates, making them difficult to scale and efficient.
Innovation Solution
An open loop solution involving a clock tree circuit, phase interpolator circuits, and digital calibration to maintain consistent latency and reduce jitter, allowing for improved bandwidth and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL/DLL circuitry is used to maintain constant propagation delay, then timing relationship is locked, but device complexity increases and power consumption increases
Solution Approach 1:
The patent extracts the timing adjustment function from complex PLL/DLL circuitry and implements it using simple delay elements and multiplexers. The propagation delay is adjusted by selecting different delay paths through multiplexers, eliminating the need for complex phase-locked loop or delay-locked loop circuitry while maintaining timing relationship stability.
Solution Approach 2:
The patent uses multiple copies of delay elements and multiplexers to achieve timing adjustment across different clock phases. By replicating simple delay circuits and using multiplexers to select appropriate delay paths, the system achieves reliable timing without complex feedback-based PLL/DLL circuitry.
2Reliability
If PLL/DLL is used to lock timing relationship, then propagation delay is maintained constant, but power consumption increases
Solution Approach 1:
The patent removes the power-intensive PLL/DLL circuitry and replaces it with simple combinatorial logic consisting of delay elements and multiplexers. The timing adjustment is achieved by selectively enabling different delay paths based on calibration results, consuming minimal power compared to continuous operation of feedback-based locking circuitry.
Solution Approach 2:
The patent performs timing calibration in advance during initialization or training phase, storing the optimal delay settings in lookup tables or calibration registers. During normal operation, pre-calibrated delay values are used without requiring continuous feedback and adjustment, significantly reducing power consumption while maintaining propagation delay consistency.
3Reliability
If DLL/PLL solution is used for phase alignment, then timing is locked, but bandwidth is limited at high data rates
Solution Approach 1:
The patent extracts the phase alignment function from bandwidth-limited PLL/DLL circuitry and implements it using fast combinatorial logic with multiplexers and delay elements. This approach eliminates the bandwidth constraints of feedback-based locking circuitry, enabling support for high data rates up to DDR5 and beyond while maintaining accurate phase alignment through pre-calibrated delay settings.
4Reliability
If conventional circuitry with multiple clock phases is used, then timing relationship is maintained, but manufacturing precision requirements increase
Solution Approach 1:
The patent removes complex multi-phase clock generation circuitry and replaces it with simple delay elements and multiplexers that operate on a single clock phase. By using combinatorial logic instead of synchronous multi-phase circuitry, the design becomes much less sensitive to process variations and manufacturing tolerances, improving robustness across different fabrication processes.
Data Source
AI summary
An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.