Open-Loop Defect Detection Circuit for Semiconductor Die Cracks
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in detecting cracks in semiconductor dies during cutting and packaging, leading to yield impact from defective products.
Innovation Solution
A semiconductor device with a defect detection circuit incorporating a plurality of latch circuits and defect detection conduction paths forms an open conduction loop to thoroughly detect crack penetration, using a test control circuit for write and read operations to identify defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a simple inspection method is used, then the manufacturing process is fast and simple, but the detectability of crack penetration is insufficient
Solution Approach 1:
The defect detection circuit is segmented into multiple latch circuits (first latch circuit, second latch circuit, third latch circuit, fourth latch circuit) arranged in a specific pattern. Each latch circuit independently detects defects in different regions, allowing the system to achieve comprehensive crack penetration detection while maintaining modular simplicity in each individual circuit unit.
Solution Approach 2:
The latch circuits are arranged in both row and column directions, creating a two-dimensional detection network. This dimensional arrangement allows the circuit to detect cracks penetrating in different orientations (horizontal and vertical) simultaneously, enhancing detectability without requiring separate detection systems for each direction.
2Measurement precision
If multiple detection paths are used to detect various types of cracks, then the detectability is enhanced, but the device complexity increases
Solution Approach 1:
Each latch circuit serves multiple functions: it detects cracks in its specific region, contributes to the overall crack penetration detection network, and can identify both horizontal and vertical crack orientations. This multi-functionality allows the system to detect various types of cracks using a unified circuit architecture rather than requiring separate specialized detectors for each crack type.
Solution Approach 2:
Multiple detection functions are merged into a single integrated defect detection circuit. The latch circuits are interconnected through conduction paths to form a unified detection system that simultaneously monitors multiple regions and crack orientations, reducing the need for separate detection systems and simplifying the overall device architecture.
3Reliability
If a comprehensive defect detection system is implemented, then yield impact is reduced, but the manufacturing cost increases
Solution Approach 1:
The defect detection circuit uses the existing semiconductor device structures (conduction paths, transistor gates) as part of the detection mechanism. The conduction paths that are already present in the device for normal operation are utilized as test paths for defect detection, eliminating the need for entirely separate test structures and reducing additional manufacturing complexity.
Solution Approach 2:
The defect detection circuit is integrated into the device structure during the manufacturing process, before the device is fully assembled and tested. This preliminary integration allows defects to be detected early in the manufacturing process, enabling timely identification and removal of defective devices, thereby reducing yield impact without requiring complex post-manufacturing testing systems.
Data Source
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AI summary
A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop.