Open-Loop Delay Locked Loop for Faster Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay locked loops (DLLs) in semiconductor memory devices require multiple feedback operations to achieve synchronization, leading to prolonged delay locking time and high current consumption.
Innovation Solution
The proposed DLL incorporates a delay pulse generation unit, a coding unit, and a delay line to generate and adjust a delay pulse, allowing for faster delay locking and reduced current consumption through an open loop structure, using a divided clock signal to minimize noise sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional closed loop DLL structure is used to achieve clock synchronization, then the delay locking can be achieved through feedback operation, but the delay locking time is prolonged and current consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay values in a delay value storage unit before actual clock synchronization is needed. The delay calculation unit computes the required delay amount based on frequency information beforehand, so when synchronization is required, the pre-computed delay value can be immediately applied without requiring multiple feedback iterations, thus reducing delay locking time while maintaining synchronization reliability
Solution Approach 2:
The patent introduces an intermediary mechanism by adding a frequency information acquisition unit and delay calculation unit that act as mediators between the reference clock and the feedback loop. These intermediaries pre-process the synchronization requirements and provide optimized delay values to the variable delay unit, reducing the burden on the feedback loop and enabling faster locking without sacrificing synchronization accuracy
2Reliability
If a conventional closed loop DLL structure is used to achieve clock synchronization, then the delay locking can be achieved through feedback operation, but current consumption increases
Solution Approach 1:
The patent reduces current consumption by performing delay calculations in advance using the frequency information acquisition unit and delay calculation unit. By pre-computing the required delay values and storing them, the system avoids the need for continuous high-power feedback operations, thereby reducing overall current consumption while maintaining reliable clock synchronization
Solution Approach 2:
The patent implements self-service by enabling the DLL to autonomously determine and apply optimal delay values through the delay calculation unit, which computes delays based on acquired frequency information without requiring extensive feedback iterations. This self-determination capability reduces the operational burden on the feedback loop and associated current consumption
3Reliability
If multiple feedback operations are performed to achieve delay locking, then clock synchronization is achieved, but the operation complexity increases
Solution Approach 1:
The patent simplifies operational complexity by pre-computing delay values through the delay calculation unit before synchronization operations are needed. This preliminary computation eliminates the need for multiple complex feedback iterations, reducing the number of operational steps required while maintaining reliable clock synchronization
Data Source
AI summary
A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.