Open-Loop MMIC Voltage Control Circuitry for Radar Systems
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Solution Overview
Problem
Conventional radar systems using monolithic microwave integrated circuits (MMICs) for frequency modulation suffer from design complexity, high power consumption, large area consumption, and susceptibility to power supply noise due to the use of discrete phase-locked loops for controlling voltage-controlled oscillators.
Innovation Solution
An open-loop circuitry using a delta-sigma modulator, decimation filter, and parallel-to-serial converter is employed to generate a voltage for controlling MMICs, reducing power consumption and susceptibility to noise while maintaining high signal-to-noise ratios by converting high-speed bit streams into analog voltages using low-pass filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discrete phase-locked loop is used to control the MMIC, then the frequency modulation can be achieved, but the design complexity increases
Solution Approach 1:
The patent extracts the feedback mechanism from the discrete PLL and implements an open-loop solution using a sequence generator that directly generates the control sequence without requiring phase detection and feedback adjustment, thereby reducing design complexity while maintaining frequency modulation capability
Solution Approach 2:
The patent replaces the mechanical feedback-based PLL system with a digital open-loop sequence generation system that uses a sequence generator and delta-sigma modulator to produce the control signal, eliminating the need for complex feedback circuits
2Reliability
If a discrete phase-locked loop is used to control the MMIC, then the frequency modulation can be achieved, but the power consumption increases
Solution Approach 1:
The patent removes the power-intensive feedback mechanisms and charge pump circuits from the PLL system, replacing them with a low-power open-loop sequence generator that directly produces the control signal without requiring continuous feedback adjustment
Solution Approach 2:
The patent uses periodic sequence generation with delta-sigma modulation to create the control signal, which allows for more efficient power consumption compared to continuous feedback operation in traditional PLLs
3Reliability
If a discrete phase-locked loop is used to control the MMIC, then the frequency modulation can be achieved, but the area consumption increases
Solution Approach 1:
The patent extracts and removes the large-area components of the PLL system such as the charge pump, phase frequency detector, and feedback circuits, replacing them with a compact open-loop sequence generator implementation
Solution Approach 2:
The patent merges the sequence generation and modulation functions into a single integrated open-loop system, eliminating the need for separate PLL components and reducing overall area consumption
4Ease of operation
If general purpose inputs/outputs are used for PLL control, then the implementation is simplified, but the susceptibility to power supply noise increases
Solution Approach 1:
The patent extracts the control signal generation from the general-purpose I/O interface and implements a dedicated open-loop sequence generator that produces the control signal internally, eliminating the susceptibility to power supply noise that affects GPIO-based implementations
Solution Approach 2:
The patent introduces a delta-sigma modulator as an intermediary between the sequence generator and the MMIC control input, which converts the digital sequence into a noise-shaped analog signal that is less susceptible to power supply noise
Data Source
AI summary
In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.