Open-Loop Pipelined ADC Stages for Lower-Power Residue Amplification
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Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) face challenges in reducing power consumption and size while maintaining high resolution and speed, as they require substantial power due to closed-loop residue amplifiers and occupy significant space in integrated circuits.
Innovation Solution
Implementing an open-loop pipelined ADC stage with a feedback transistor-follower combination and current mirror to set the summation node voltage equal to the sample-and-hold voltage, mirroring currents to set output voltages, and using a clamping circuit to manage transient conditions, thereby reducing power consumption and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If closed-loop residue amplifiers are used in pipelined ADC stages, then high digital resolution and speed are achieved, but power consumption increases substantially
Solution Approach 1:
The ADC is divided into multiple pipeline stages, where only the first stage uses a closed-loop residue amplifier for high precision, while subsequent stages use open-loop residue amplifiers. This segmentation allows the system to achieve high overall resolution while reducing power consumption in the later stages that require less precision.
Solution Approach 2:
Different residue amplifier configurations are applied to different stages based on their specific requirements. The first stage uses a closed-loop configuration for high precision, while subsequent stages use open-loop configurations. This local differentiation optimizes the balance between resolution and power consumption for each stage's specific function.
2Measurement precision
If closed-loop residue amplifiers are used in pipelined ADC stages, then high digital resolution is achieved, but the circuit occupies significant space in integrated circuits
Solution Approach 1:
The ADC architecture segments the residue amplifier requirements across stages, placing the power-intensive and area-intensive closed-loop amplifier only in the first stage. Subsequent stages use compact open-loop amplifiers, reducing the total circuit area while maintaining high resolution through the pipelined architecture.
Solution Approach 2:
The circuit area is optimized by applying different amplifier topologies to different stages. The first stage receives the full closed-loop amplifier treatment for maximum precision, while subsequent stages use simplified open-loop designs, creating a local quality distribution that minimizes total area while achieving the required resolution.
3Use of energy by moving object
If open-loop residue amplifiers are used in pipelined ADC stages, then power consumption and size are reduced, but maintaining high digital resolution becomes challenging
Solution Approach 1:
The system segments the resolution requirements across multiple stages, with the first stage handling the most significant bits using a closed-loop amplifier for high precision. Subsequent stages handle less significant bits using open-loop amplifiers, where the reduced precision requirement allows for lower power consumption while maintaining overall high resolution.
Solution Approach 2:
The pipelined architecture ensures continuous conversion operation across stages. Each stage processes a portion of the conversion continuously, with the open-loop stages maintaining sufficient precision for their designated bit positions while enabling uninterrupted high-speed conversion throughout the pipeline.
Data Source
AI summary
One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.