Open-Loop Data Buffer and RCD Timing Alignment Without PLL/DLL
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Solution Overview
Problem
Conventional solutions for maintaining constant propagation delay in DDR4 and DDR5 memory interfaces, such as using phase-locked loops (PLL) or delay-locked loops (DLL), are complex, power-intensive, and face bandwidth limitations, especially at higher data rates like 4.4 GHz and 6.6 GHz, making it difficult to scale down process sizes and maintain timing accuracy.
Innovation Solution
An open loop circuit and delay circuit configuration that generates an in-phase clock signal and adjusts data signal delay to maintain latency within a pre-defined range, eliminating the need for PLL/DLL and reducing power consumption by using digital calibration to align strobe and data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL or DLL circuitry is used to maintain constant propagation delay, then timing relationship is locked and tPDM is kept constant, but device complexity increases and power consumption increases
Solution Approach 1:
The patent extracts and removes the PLL/DLL circuitry from the memory interface, replacing it with an open-loop delay adjustment mechanism. This eliminates the complex feedback loops and phase detection circuits while maintaining timing stability through direct delay control of the strobe signal path.
Solution Approach 2:
The timing control is segmented into separate delay adjustment stages for different signal paths (strobe and data). Independent delay elements allow precise control of each path without requiring synchronized feedback mechanisms, simplifying the overall circuit architecture.
2Reliability
If conventional PLL or DLL circuitry is used to maintain constant propagation delay, then timing relationship is locked and tPDM is kept constant, but power consumption increases
Solution Approach 1:
The patent removes the power-intensive PLL/DLL feedback mechanisms and replaces them with static delay elements controlled by calibration circuits. This eliminates continuous oscillation and phase detection power consumption while maintaining timing stability.
Solution Approach 2:
Delay calibration is performed in advance during initialization or training phases, storing optimal delay values in lookup tables. During normal operation, pre-calibrated delay settings are applied without requiring continuous active feedback, significantly reducing power consumption while maintaining timing accuracy.
3Reliability
If conventional PLL or DLL circuitry is used, then timing relationship is maintained, but loop bandwidth is limited causing design challenges at 4.4 GHz, 6.6 GHz and higher data rates
Solution Approach 1:
The patent removes the feedback loop entirely, eliminating bandwidth limitations inherent in PLL/DLL designs. The open-loop architecture allows delay adjustment to keep pace with increasing data rates without being constrained by loop stability requirements.
Solution Approach 2:
The delay elements are designed to be dynamically adjustable through calibration circuits that can adapt delay values based on operating conditions and data rate. This dynamic calibration capability enables the system to maintain timing stability across a wide range of speeds without requiring high-bandwidth feedback loops.
4Reliability
If conventional circuitry uses PLL/DLL internally for phase alignment, then timing is locked, but scaling down process size becomes difficult
Solution Approach 1:
The patent removes the PLL/DLL infrastructure that becomes increasingly difficult to implement at smaller process nodes. The open-loop delay control approach is more amenable to scaling as it avoids the complex transistor-level feedback mechanisms that are sensitive to process variations at advanced nodes.
Solution Approach 2:
The patent replaces the mechanical feedback-based phase locking mechanism with a digital calibration and delay adjustment system. This substitution allows for easier integration and scaling in modern CMOS processes where digital calibration circuits can be more effectively implemented than analog feedback loops.
5Reliability
If conventional PLL/DLL solutions are used, then timing relationship is maintained, but the solution is very complicated with many clock phases that need to be generated
Solution Approach 1:
The patent removes the multi-phase clock generation infrastructure required by PLL/DLL solutions. Instead, a single system clock is used in conjunction with delay-adjusted strobe signals, eliminating the need for multiple phase-shifted clock domains and their associated synchronization complexity.
Data Source
AI summary
An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.