Open Stubs for Signal Integrity in Multi-Layer Substrates

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Solution Overview

Problem

The increasing demand for miniaturization and capacity in electronic devices is not met by the current semiconductor memory chips, leading to reduced time margins due to the need for more chips connected to a single channel, resulting in decreased performance.

Innovation Solution

An electronic apparatus with a base substrate featuring multiple layers and wiring layers, including signal and ground wiring layers, and open stubs connected via vias to improve signal transmission efficiency between semiconductor chips, reducing signal distortion and enhancing time margins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of semiconductor memory chips connected to one channel is increased to meet capacity demands, then the storage capacity is improved, but the time margin decreases

Engineering Contradiction:
Improvenumber of semiconductor memory chipsVSAvoidtime margin
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent introduces open stubs as intermediary elements connected to signal lines via vias. These stubs act as mediators that reflect signals back toward the source, compensating for signal degradation and distortion that occurs when multiple chips are connected in series. This allows more chips to be connected while maintaining adequate signal quality and time margin.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the signal transmission parameters by adding open stubs that change the electrical characteristics of the signal line. The stubs create impedance variations that reflect signals constructively, effectively changing the transmission characteristics to accommodate longer signal paths through multiple chips without degrading time margin.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If multiple wiring layers are used to connect chips, then the connectivity is improved, but the signal distortion increases

Engineering Contradiction:
ImproveconnectivityVSAvoidsignal distortion
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The open stubs serve as intermediary elements that compensate for signal distortion introduced by multiple wiring layers. By strategically placing stubs at specific locations and connecting them via vias, the system counteracts the harmful effects of signal degradation caused by traversing multiple layers, thereby maintaining signal integrity while preserving connectivity flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If open stubs are added to compensate for signal distortion, then the time margin is improved, but the device complexity increases

Engineering Contradiction:
Improvetime marginVSAvoidstructure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent achieves time margin improvement through parameter changes in the existing wiring structure by adding open stubs. While this does increase structural complexity, the stubs can be integrated into existing wiring layers and connected via standard vias, minimizing the increase in manufacturing complexity while effectively compensating for signal distortion and improving time margin.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11064603B2Electronic apparatus having package base substrate
Publication Date: 2021.07.13 SAMSUNG ELECTRONICS CO LTD
  • US11064603B2 patent drawing
  • US11064603B2 patent drawing
  • US11064603B2 patent drawing

AI summary

Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.